https://scholars.lib.ntu.edu.tw/handle/123456789/372969
標題: | Transport-layer assisted vertical traffic balanced routing for thermal-aware three-dimensional Network-on-Chip systems | 作者: | Chen, K.-C. Chih-Hao Lin, S.-Y. Hung, H.-S. Wu, A.-Y. AN-YEU(ANDY) WU |
公開日期: | 2012 | 來源出版物: | International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 | 摘要: | The thermal problem of three-dimensional Network-on-Chip (3D NoC) is severer than 2D NoC because chip stacking. To keep the temperature below a certain thermal limit, the near-overheat routers are throttled and the 3D topology becomes Non-Stationary Irregular Mesh (NSI-Mesh). To ensure the successful packet delivery in the NSI-Mesh, Transport Layer Assisted Routing (TLAR) scheme was proposed. It has better performance than the conventional routing approaches for NSI-Mesh. However, it still suffers significant traffic congestion in the bottom chip layer and extremely traffic unbalance between vertical chip layers. In this paper, we propose a transport layer assisted Vertical Traffic Balance Routing (VTBR) scheme. It can be applied to any routing approaches for NSI-Mesh. The experimental results show that the proposed VTBR can achieve more balanced traffic in the vertical direction and improve 35.3% 40% network throughput. © 2012 IEEE. |
URI: | http://www.scopus.com/inward/record.url?eid=2-s2.0-84864053254&partnerID=MN8TOARS http://scholars.lib.ntu.edu.tw/handle/123456789/372969 |
DOI: | 10.1109/VLSI-DAT.2012.6212626 | SDG/關鍵字: | 3D topology; Balanced traffic; Chip stacking; Conventional routing; Irregular meshes; Network on chip; Network throughput; Network-on-chip systems; Nonstationary; Packet Delivery; Routing approach; Thermal limits; Traffic balance; Traffic unbalance; Transport layers; Vertical direction; Servers; Three dimensional; Traffic congestion; VLSI circuits; Routers |
顯示於: | 電機工程學系 |
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