https://scholars.lib.ntu.edu.tw/handle/123456789/387033
標題: | A 6-bit 1-GS/s Two-Step SAR ADC in 40-nm CMOS | 作者: | Tai, H.-Y. Tsai, C.-H. Tsai, P.-Y. Chen, H.-W HSIN-SHU CHEN |
關鍵字: | Analog-to-digital converter (ADC); duty-cycle clock generator; source follower (SF); successive approximation; two-step | 公開日期: | 2014 | 卷: | 61 | 期: | 5 | 起(迄)頁: | 339-343 | 來源出版物: | IEEE Transactions on Circuits and Systems II: Express Briefs | 摘要: | This brief presents a single-channel two-step successive approximation register (SAR) analog-to-digital converter (ADC) using a source follower as an interstage residue amplifier. An asynchronous SAR ADC with two-step timing can effectively allocate the bit-resolving procedure into the whole clock period and eliminate a dedicated duty-cycle clock generator. The arbitrary weight capacitor array technique is utilized to tolerate offset mismatch between the coarse and fine stages. The level-shift technique is used to accelerate the comparator. The ADC in 40-nm CMOS obtains 5.6 and 4.9 effective numbers of bits at Nyquist with the conversion rate of 800 MS/s and 1 GS/s, respectively. It consumes 5.3 mW at 1 GS/s and achieves a figure of merit of 180 fJ/conversion-step. The core circuit occupies an area of 0.009 mm2. © 2004-2012 IEEE. |
URI: | https://www.scopus.com/inward/record.uri?eid=2-s2.0-84901369744&doi=10.1109%2fTCSII.2014.2312642&partnerID=40&md5=522b9d8d4e7e886408ee56177cf34062 http://scholars.lib.ntu.edu.tw/handle/123456789/387033 |
DOI: | 10.1109/TCSII.2014.2312642 |
顯示於: | 電機工程學系 |
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