https://scholars.lib.ntu.edu.tw/handle/123456789/387313
標題: | VLSI architecture design of guided filter for 30 frames/s full-HD Video | 作者: | Kao, C.-C. Lai, J.-H. SHAO-YI CHIEN |
關鍵字: | Double integral image architecture; guided filter; integral image | 公開日期: | 2014 | 卷: | 24 | 期: | 3 | 起(迄)頁: | 513-524 | 來源出版物: | IEEE Transactions on Circuits and Systems for Video Technology | 摘要: | Filtering is widely used in image and video processing for various applications. Recently, the guided filter has been proposed and became one of the popular filtering methods. In this paper, to achieve the computation demand of guided filtering in full-HD video, a double integral image architecture for guided filter ASIC design is proposed. In addition, a reformation of the guided filter formula is proposed, which can prevent the error resulted from truncation in the fractional part and modify the regularization parameter on user's demand. The hardware architecture of the guided image filter is then proposed and can be embedded in mobile devices to achieve real-time HD applications. To the best of our knowledge, this paper is also the first ASIC design for guided image filter. With a TSMC 90-nm cell library, the design can operate at 100 MHz and support for Full-HD (1920 ×, 1080) 30 frame/s with 92.9K gate counts and 3.2 KB on-chip memory. Moreover, for the hardware efficiency, our architecture is also the best compared to other previous works with bilateral filter. © 2014 IEEE. |
URI: | http://www.scopus.com/inward/record.url?eid=2-s2.0-84896532945&partnerID=MN8TOARS http://scholars.lib.ntu.edu.tw/handle/123456789/387313 |
ISSN: | 10518215 | DOI: | 10.1109/TCSVT.2013.2278145 | SDG/關鍵字: | Hardware; Integrated circuits; Mobile devices; Double integrals; Guided filters; Hardware architecture; Hardware efficiency; Image and video processing; Integral images; Regularization parameters; VLSI architectures; Video signal processing |
顯示於: | 電子工程學研究所 |
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