https://scholars.lib.ntu.edu.tw/handle/123456789/387325
標題: | Routability-driven blockage-aware macro placement | 作者: | Chen, Y.-F. Huang, C.-C. Chiou, C.-H. Wang, C.-J. YAO-WEN CHANG |
關鍵字: | Physical Design; Placement; Routability | 公開日期: | 2014 | 來源出版物: | Design Automation Conference | 摘要: | We present a new floorplan representation, called circular-packing trees (CP-trees), for the problem of macro placement. Our CPtrees can flexibly pack movable macros toward corners or preplaced macros along chip boundaries circularly to optimize macro positions/orientations for better wirelength and routing congestion. Unlike previous macro placers that often consider only the interconnections among macros, we develop a routability-aware wirelength model to fast estimate the wirelength among macros and standard cells and to consider macro porosity effects for better routability. Compared with leading academic mixed-size placers, experimental results show that our algorithm can achieve the shortest routed wirelength for industrial benchmarks. Copyright 2014 ACM. |
URI: | http://www.scopus.com/inward/record.url?eid=2-s2.0-84903138338&partnerID=MN8TOARS http://scholars.lib.ntu.edu.tw/handle/123456789/387325 |
ISSN: | 0738100X | DOI: | 10.1145/2593069.2593206 | SDG/關鍵字: | Computer aided design; Chip boundaries; Macro-porosity; Physical design; Placement; Routability; Routing congestion; Standard cell; Wire length; Forestry; Algorithms; Cad Cam; Forestry; Problem Solving |
顯示於: | 電子工程學研究所 |
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