https://scholars.lib.ntu.edu.tw/handle/123456789/394735
DC Field | Value | Language |
---|---|---|
dc.contributor.author | G.-Y. Lin | en_US |
dc.contributor.author | K.-H. Tsai | en_US |
dc.contributor.author | J.-L. Huang | en_US |
dc.contributor.author | W.-T. Cheng | en_US |
dc.contributor.author | JIUN-LANG HUANG | zz |
dc.creator | G.-Y. Lin;K.-H. Tsai;J.-L. Huang;W.-T. Cheng | - |
dc.date.accessioned | 2018-09-10T15:26:16Z | - |
dc.date.available | 2018-09-10T15:26:16Z | - |
dc.date.issued | 2015-01 | - |
dc.identifier.uri | http://scholars.lib.ntu.edu.tw/handle/123456789/394735 | - |
dc.language | en | en |
dc.relation.ispartof | International Symposium on VLSI Design, Automation, and Test | en_US |
dc.source | AH-anncc | - |
dc.title | A Test-Application-Count Based Learning Technique for Test Time Reduction | - |
dc.type | conference paper | en |
dc.identifier.doi | 10.1109/VLSI-DAT.2015.7114507 | - |
dc.identifier.scopus | 2-s2.0-84936980470 | - |
item.fulltext | no fulltext | - |
item.cerifentitytype | Publications | - |
item.openairetype | conference paper | - |
item.openairecristype | http://purl.org/coar/resource_type/c_5794 | - |
item.grantfulltext | none | - |
crisitem.author.dept | Electronics Engineering | - |
crisitem.author.dept | Electrical Engineering | - |
crisitem.author.dept | Program in Integrated Circuit Design and Automation | - |
crisitem.author.orcid | 0000-0002-9425-3855 | - |
crisitem.author.parentorg | College of Electrical Engineering and Computer Science | - |
crisitem.author.parentorg | College of Electrical Engineering and Computer Science | - |
crisitem.author.parentorg | Graduate School of Advanced Technology | - |
Appears in Collections: | 電子工程學研究所 |
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