https://scholars.lib.ntu.edu.tw/handle/123456789/427752
標題: | Overview of High-Efficiency Ant Colony Optimization (ACO)-based Adaptive Routings for Traffic Balancing in Network-on-Chip Systems | 作者: | En-Jui Chang An-Yeu (Andy) Wu AN-YEU(ANDY) WU 吳安宇 |
公開日期: | 2017 | 來源出版物: | IEEE 12th International Conference on ASIC (ASICON-2017) | 摘要: | The regular topology of mesh-based Network-on-Chip (NoC) provides flexible and scalable architecture for chip multiprocessor (CMP) systems. However, as the complexity of the network increases, the traffic congestion problems become major performance bottlenecks. An effective adaptive routing algorithm can help minimize path congestion through load balancing. However, conventional adaptive routing schemes only use current channel-based information to detect the congestion status. This information has difficulty showing the real congestion status under time-variant traffic patterns. To predict temporal network congestion, Ant Colony Optimization (ACO) based routing was proposed to identify the near-future non-congested path to a desired target according to historical network information. To design a high-efficiency ACO-based routing for traffic balancing in resource-limited NoCs, two major design issues should be considered, including 1) the selection efficiency and 2) the cost efficiency. In this paper, the design challenges and concepts of ACO-based adaptive routings are introduced. Besides, the representative related works are reviewed and summarized. Finally, we conclude the paper and point out the future works of ACO-based routing algorithms. © 2017 IEEE. |
URI: | https://scholars.lib.ntu.edu.tw/handle/123456789/427752 | ISSN: | 21627541 | DOI: | 10.1109/asicon.2017.8252416 | SDG/關鍵字: | Ant colony optimization; Artificial intelligence; Binary alloys; Efficiency; Network-on-chip; Servers; Traffic congestion; Adaptive routing algorithm; Ant Colony Optimization (ACO); Chip multiprocessors; Congestion problem; Mesh-based networks; Network information; Performance bottlenecks; Scalable architectures; Integrated circuit design |
顯示於: | 電機工程學系 |
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