https://scholars.lib.ntu.edu.tw/handle/123456789/428205
標題: | An Ultra-low Power 169-nA 32.768-kHz Fractional-N PLL | 作者: | C.-Y. Lin T.-J. Wang T.-H. Liu T.-H. Lin TSUNG-HSIEN LIN 林宗賢 |
公開日期: | 2017 | 來源出版物: | IEEE A-SSCC | 摘要: | This paper presents an ultra-low power 32.768-kHz fractional-N phase-locked loop (PLL). Several circuit techniques are adopted to facilitate low-power operation. A duty-cycled control scheme is proposed to turn off the charge pump intermittently for energy saving. In the VCO, a near-off switch is applied to implement a large resistor, leading to a lower power consumption and smaller chip area. Furthermore, the digital power consumption is reduced by operating the digital circuits at a lower supply voltage generated from an on-chip voltage regulator. This PLL is fabricated in the TSMC 180-nm CMOS process with a core area of 0.116 mm2. Its current consumption is 169 nA from a 1-V supply. The measured peak-to-peak cycle-to-cycle jitter is 529.4 ns. © 2017 IEEE. |
URI: | https://scholars.lib.ntu.edu.tw/handle/123456789/428205 | DOI: | 10.1109/asscc.2017.8240212 | SDG/關鍵字: | Electric power utilization; Energy conservation; Phase locked loops; Transceivers; Voltage regulators; Circuit techniques; Current consumption; Cycle-to-cycle jitter; Fractional-N phase-locked loops; Fractional-N PLL; Low-power operation; Lower-power consumption; On-chip voltage regulator; Low power electronics |
顯示於: | 電子工程學研究所 |
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