https://scholars.lib.ntu.edu.tw/handle/123456789/489907
標題: | Write-Aware Memory Management for Hybrid SLC-MLC PCM Memory Systems | 作者: | Ho, Chien-Chung Chang, Yu-Ming Chang, Yuan-Hao Chen, Hsiu-Chang TEI-WEI KUO |
公開日期: | 2017 | 卷: | 17 | 期: | 2 | 起(迄)頁: | 16-26 | 來源出版物: | Applied Computing Review | 摘要: | Replacing the traditional volatile main memory, e.g., DRAM, with a non-volatile phase change memory (PCM) has become a possible solution to reduce the energy consumption of computing systems. To further reduce the bit cost of PCM, the development trend of PCM goes from single-level-cell (SLC) the multi-level-cell (MLC) technology. However, the worse endurance and the intolerable long write latency hinder a MLC PCM from being used as the main memory of computing systems. In this work, we propose a memory management design to facilitate enabling the use of hybrid PCMas main memory to achieve a better trade-off between the cost and the performance of PCM-based computing systems, where the hybrid PCM is composed of SLC PCM and MLC PCM. In particular, the proposed design can be seamlessly integrated into the inherent memory management of modern operation systems without additional hardware components. The evaluation results show that the proposed design over a hybrid PCM can improve the average read/write performance for almost 10 times and extend the lifetime for more than 32 times, compared to systems with pure MLC PCM. © 2016 ACM. |
URI: | https://scholars.lib.ntu.edu.tw/handle/123456789/489907 | ISSN: | 1559-6915 | DOI: | 10.1145/2987386.2987398 | SDG/關鍵字: | Durability; Dynamic random access storage; Economic and social effects; Energy utilization; Development trends; Hardware components; Memory management; Multi level cell (MLC); Phase change memory (pcm); Read/write performance; Single level cells; Wear leveling; Phase change memory |
顯示於: | 資訊工程學系 |
在 IR 系統中的文件,除了特別指名其著作權條款之外,均受到著作權保護,並且保留所有的權利。