https://scholars.lib.ntu.edu.tw/handle/123456789/497461
標題: | A 38-GHz power amplifier with high efficiency and low quiescent power for phased array applications in 65-nm CMOS process | 作者: | Wang, H. Chou, Y.-T. Lin, J.-L. Hsiao, Y.-H. HUEI WANG |
關鍵字: | 38 GHz; CMOS; Gigh efficiency; Low quiescent power; Phased array systems; Power amplifier | 公開日期: | 2018 | 卷: | 2018-January | 起(迄)頁: | 275-278 | 來源出版物: | IEEE MTT-S International Microwave and RF Conference, IMaRC 2017 | 摘要: | This paper presents a 38-GHz power amplifier (PA) implemented in 65-nm CMOS process for phased-array applications. The design targets of the PA are medium output power and high efficiency under low dc power consumption. The proposed PA adopts the asymmetrical output stage design with the neutralization technique applied to transistors and a novel low-imbalance transformer matching for high Q-factor. The measured saturation power (PSAT) is 15.6 dBm accompanying with 31.8% peak power add efficiency (PAE) and 11.9% PAE at 6-dB back-off PAE (PAE@Psat-6dB) at 38 GHz. This PA achieves good efficiency at PSAT compared with published millimeter-wave CMOS PAs with Psat ranging from 15 to 20 dBm. © 2017 IEEE. |
URI: | https://scholars.lib.ntu.edu.tw/handle/123456789/497461 | DOI: | 10.1109/IMaRC.2017.8636647 | SDG/關鍵字: | CMOS integrated circuits; Efficiency; Energy efficiency; Integrated circuit design; Millimeter waves; Q factor measurement; 38 GHz; CMOS processs; DC power consumption; High Q factor; High-efficiency; Low quiescent power; Phased array systems; Saturation power; Power amplifiers |
顯示於: | 電機工程學系 |
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