https://scholars.lib.ntu.edu.tw/handle/123456789/497538
標題: | A K-Band adaptive-bias power amplifier with enhanced linearizer using 0.18-μm CMOS process | 作者: | Huang, T.-Y. Lin, Y.-H. Wang, H. HUEI WANG |
關鍵字: | adaptive bias; CMOS process; K-Band; power amplifier; pre-distortion linearizer | 公開日期: | 2015 | 來源出版物: | 2015 IEEE MTT-S International Microwave Symposium, IMS 2015 | 摘要: | A new topology of power amplifier (PA) is developed in 0.18-μm CMOS. The topology adopts the adaptive bias and pre-distortion linearizer simultaneously. The design of this PA takes back-off efficiency, linear output power, and quiescent power consumption into consideration. After linearization, the proposed PA achieves 6.8% PAE at 6-dB backoff from P1dB, 14.1% PAE at OP1dB, and high linear output power 9.2 dBm with third-order intermodulation distortion (IMD3) of -40 dBc. This circuit shows good performance compared with the published PAs in 0.18-μm CMOS and suitable for high data rate transmission applications. © 2015 IEEE. |
URI: | https://scholars.lib.ntu.edu.tw/handle/123456789/497538 | DOI: | 10.1109/MWSYM.2015.7166843 | SDG/關鍵字: | CMOS integrated circuits; Energy efficiency; Topology; Adaptive bias; CMOS processs; High data rate transmission; K bands; Linear output; Linearizers; Pre-distortion; Third order intermodulation distortion; Power amplifiers |
顯示於: | 電機工程學系 |
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