https://scholars.lib.ntu.edu.tw/handle/123456789/498168
標題: | A 0.3-V 7.6-fJ/conv-step delta-sigma time-to-digital converter with a gated-free ring oscillator | 作者: | Chang, C.-K. Tsai, Y.-K. Cheng, K.-H. LIANG-HUNG LU |
關鍵字: | Low power; Low voltage; Noise shaping; Oversampling; Time-domain; Time-to-digital converter (TDC) | 公開日期: | 2017 | 起(迄)頁: | 221-224 | 來源出版物: | Proceedings - 2017 IEEE 15th International New Circuits and Systems Conference, NEWCAS 2017 | 會議論文: | 15th IEEE International New Circuits and Systems Conference, NEWCAS 2017 | 摘要: | An energy efficient delta-sigma time-to-digital converter (TDC) is presented in this paper. Compared with conventional circuit techniques, non-ideal effects associated with switching noise and transistor leakage can be generally prevented due to the use of a gated-free ring oscillator and leakage-suppression switches in the circuit implementation. The proposed TDC is fabricated in 90-nm CMOS, consuming a current of 5 μA from a 0.3-V supply. With first-order shaping of the quantization noise, the circuit demonstrates an equivalent number of bits (ENOB) of 10.9 bits in 50-kHz signal bandwidth. © 2017 IEEE. |
URI: | https://scholars.lib.ntu.edu.tw/handle/123456789/498168 https://www.scopus.com/inward/record.uri?eid=2-s2.0-85034432292&doi=10.1109%2fNEWCAS.2017.8010145&partnerID=40&md5=bc5d639972db7821e9485b3f0f63c8a5 |
DOI: | 10.1109/NEWCAS.2017.8010145 | SDG/關鍵字: | Energy efficiency; Oscillators (electronic); Quantization (signal); Signal processing; Time domain analysis; Low Power; Low voltages; Noise-shaping; Over sampling; Time domain; Time to digital converters; Frequency converters |
顯示於: | 電機工程學系 |
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