|Title:||A 0.43pJ/bit true random number generator||Authors:||Kuan, T.-K.
|Issue Date:||2015||Start page/Pages:||33-36||Source:||Proceedings - 2014 IEEE Asian Solid-State Circuits Conference, A-SSCC 2014||Abstract:||
A small-area energy-efficient true random number generator (TRNG) is presented. This TRNG introduces a jitter signal generator to realize the noise pre-amplification, and utilizes a metastable latch to resolve the jitter edges. Moreover, to tolerate the process and environment variations, an offset calibration is employed to dynamically correct the bias of the probability of logic 0/1 in background. A prototype is fabricated in 40-nm CMOS technology. It occupies an area of 0.0014mm2 and consumes 214nW from a 0.8-V supply at a throughput of 500kbps. The proposed TRNG passes the NIST tests, and its calculated FOM is 0.43pJ/bit. © 2014 IEEE.
|URI:||https://scholars.lib.ntu.edu.tw/handle/123456789/499853||DOI:||10.1109/ASSCC.2014.7008853||SDG/Keyword:||Energy efficiency; Jitter; Number theory; CMOS technology; Energy efficient; Offset calibration; Small area; True randoms; Random number generation
|Appears in Collections:||電機工程學系|
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