https://scholars.lib.ntu.edu.tw/handle/123456789/499884
標題: | A 132.6-GHz phase-locked loop in 65 nm digital CMOS | 作者: | Lin, B.-Y. SHEN-IUAN LIU |
關鍵字: | Fourth-order LC ladder; injection-locked frequency divider (ILFD); phase-locked loop (PLL); voltage-controlled oscillator (VCO) | 公開日期: | 2011 | 卷: | 58 | 期: | 10 | 起(迄)頁: | 617-621 | 來源出版物: | IEEE Transactions on Circuits and Systems II: Express Briefs | 摘要: | A phase-locked loop (PLL) with the proposed voltage-controlled oscillator (VCO) and a divide-by-2 injection-locked frequency divider (ILFD) is fabricated in 65-nm digital CMOS technology. The proposed VCO and the divide-by-two ILFD operate at the higher and lower poles, respectively, of two fourth-order LC ladders. The frequency ratio between the VCO and its first divide-by-2 ILFD is kept by scaling the inductances and the capacitances. The design considerations of this VCO and the locking range of this ILFD are discussed. The measured locking range of this PLL is 132.1-132.6 GHz. It consumes 120.8 mW from 1.35-V supply, excluding the output buffers. The chip area is 0.96 × 0.92 mm 2. © 2011 IEEE. |
URI: | https://scholars.lib.ntu.edu.tw/handle/123456789/499884 https://www.scopus.com/inward/record.uri?eid=2-s2.0-80054871768&doi=10.1109%2fTCSII.2011.2164156&partnerID=40&md5=45d33364dfe7eb91bfddadc9cce97ed2 |
ISSN: | 15497747 | DOI: | 10.1109/TCSII.2011.2164156 | SDG/關鍵字: | Capacitance; Circuit oscillations; CMOS integrated circuits; Ladders; Oscillistors; Phase locked loops; Variable frequency oscillators; Voltage dividers; Design considerations; Digital CMOS technology; Frequency ratios; Injection Locked Frequency Divider(ILFD); LC ladders; Locking range; Output Buffer; Phase Locked Loop (PLL); Frequency dividing circuits |
顯示於: | 電機工程學系 |
在 IR 系統中的文件,除了特別指名其著作權條款之外,均受到著作權保護,並且保留所有的權利。