|Title:||A 0.035-pJ/bit/dB 20-Gb/s Adaptive Linear Equalizer with an Adaptation Time of 2.68 μs||Authors:||Chen, K.-Y.
|Keywords:||Adaptive equalizer; asynchronous sampling; fast converging; linear equalizer||Issue Date:||2017||Journal Volume:||64||Journal Issue:||6||Start page/Pages:||645-649||Source:||IEEE Transactions on Circuits and Systems II: Express Briefs||Abstract:||
A 20-Gb/s adaptive linear equalizer with a coefficient fast-converging method is presented. By using the asynchronous sampling technique, the power dissipation of the circuits, realizing the adaptation method, can be reduced. However, the equalization coefficients require a considerable amount of time to be determined. To shorten the asynchronous sampling time, the high-frequency gain of the linear equalizer is calibrated prior to the low-frequency one. With a 20-Gb/s pseudorandom binary sequence of 27-1, the measured bit-error-rates are all less than 10-12 for channel loss from-7.98 to-18.3 dB. Moreover, the equalization coefficients are determined within 2.68 μs . Fabricated in a 40-nm CMOS technology, this equalizer totally consumes 12.8 mW from a 1.1-V supply, of which only 4.9 mW dissipates in the circuits, realizing the proposed method. The calculated figure-of-merit is 0.035-pJ/bit/dB. © 2004-2012 IEEE.
|ISSN:||15497747||DOI:||10.1109/TCSII.2016.2599528||SDG/Keyword:||Binary sequences; Adaptation methods; Adaptive equalizer; Asynchronous sampling; fast converging; Figure of merits; High frequency gain; Linear equalizer; Pseudo-random binary sequences; Equalizers|
|Appears in Collections:||電機工程學系|
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