https://scholars.lib.ntu.edu.tw/handle/123456789/502018
標題: | Multilevel routing with antenna avoidance. | 作者: | Ho, Tsung-Yi SAO-JIE CHEN YAO-WEN CHANG |
關鍵字: | Design for manufacturability (DFM); Multilevel optimization; Nanometer; Physical design; Process antenna effect; Routing | 公開日期: | 2004 | 起(迄)頁: | 34-40 | 來源出版物: | Proceedings of the International Symposium on Physical Design | 摘要: | As technology advances into the nanometer territory, the antenna problem has caused significant impact on routing tools. The antenna effect is a phenomenon of plasma-induced gate oxide degradation caused by charge accumulation on conductors. It directly influences manufacturability and yield of VLSI circuits, especially in deep-submicron technology using high density plasma. Furthermore, the continuous increase of the problem size of IC routing is also a great challenge to existing routing algorithms. In this paper, we propose a novel framework for multilevel full-chip routing with antenna avoidance using a built-in jumper insertion approach. Experimental results show that our approach reduced antenna-violated gates by about 98% and also achieved 100% routing completion for all circuits. |
URI: | https://scholars.lib.ntu.edu.tw/handle/123456789/502018 https://www.scopus.com/inward/record.uri?eid=2-s2.0-2942641881&doi=10.1145%2f981066.981074&partnerID=40&md5=d4dd8566fef83b0a38d799f2e9ecd2e8 |
DOI: | 10.1145/981066.981074 | SDG/關鍵字: | Antennas; Computer aided design; Gates (transistor); Integrated circuit layout; Microprocessor chips; Routers; Design for manufacturability (DFM); Physical design; Process antenna effects; Routing; VLSI circuits |
顯示於: | 電信工程學研究所 |
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