https://scholars.lib.ntu.edu.tw/handle/123456789/502018
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Ho, Tsung-Yi | en_US |
dc.contributor.author | SAO-JIE CHEN | en_US |
dc.contributor.author | YAO-WEN CHANG | - |
dc.creator | Ho, Tsung-Yi;Chang, Yao-Wen;Chen, Sao-Jie | - |
dc.date.accessioned | 2020-06-16T06:31:41Z | - |
dc.date.available | 2020-06-16T06:31:41Z | - |
dc.date.issued | 2004 | - |
dc.identifier.uri | https://scholars.lib.ntu.edu.tw/handle/123456789/502018 | - |
dc.identifier.uri | https://www.scopus.com/inward/record.uri?eid=2-s2.0-2942641881&doi=10.1145%2f981066.981074&partnerID=40&md5=d4dd8566fef83b0a38d799f2e9ecd2e8 | - |
dc.description.abstract | As technology advances into the nanometer territory, the antenna problem has caused significant impact on routing tools. The antenna effect is a phenomenon of plasma-induced gate oxide degradation caused by charge accumulation on conductors. It directly influences manufacturability and yield of VLSI circuits, especially in deep-submicron technology using high density plasma. Furthermore, the continuous increase of the problem size of IC routing is also a great challenge to existing routing algorithms. In this paper, we propose a novel framework for multilevel full-chip routing with antenna avoidance using a built-in jumper insertion approach. Experimental results show that our approach reduced antenna-violated gates by about 98% and also achieved 100% routing completion for all circuits. | - |
dc.relation.ispartof | Proceedings of the International Symposium on Physical Design | - |
dc.subject | Design for manufacturability (DFM); Multilevel optimization; Nanometer; Physical design; Process antenna effect; Routing | - |
dc.subject.other | Antennas; Computer aided design; Gates (transistor); Integrated circuit layout; Microprocessor chips; Routers; Design for manufacturability (DFM); Physical design; Process antenna effects; Routing; VLSI circuits | - |
dc.title | Multilevel routing with antenna avoidance. | en_US |
dc.type | conference paper | en |
dc.identifier.doi | 10.1145/981066.981074 | - |
dc.identifier.scopus | 2-s2.0-2942641881 | - |
dc.identifier.url | https://doi.org/10.1145/981066.981074 | - |
dc.relation.pages | 34-40 | - |
item.cerifentitytype | Publications | - |
item.fulltext | no fulltext | - |
item.openairecristype | http://purl.org/coar/resource_type/c_5794 | - |
item.openairetype | conference paper | - |
item.grantfulltext | none | - |
crisitem.author.dept | Electrical Engineering | - |
crisitem.author.dept | Electronics Engineering | - |
crisitem.author.dept | Electrical Engineering | - |
crisitem.author.dept | Computer Science and Information Engineering | - |
crisitem.author.dept | Center for Information and Electronics Technologies | - |
crisitem.author.dept | MediaTek-NTU Research Center | - |
crisitem.author.orcid | 0000-0003-1152-171X | - |
crisitem.author.orcid | 0000-0002-0564-5719 | - |
crisitem.author.parentorg | College of Electrical Engineering and Computer Science | - |
crisitem.author.parentorg | College of Electrical Engineering and Computer Science | - |
crisitem.author.parentorg | College of Electrical Engineering and Computer Science | - |
crisitem.author.parentorg | College of Electrical Engineering and Computer Science | - |
crisitem.author.parentorg | Others: University-Level Research Centers | - |
crisitem.author.parentorg | Others: University-Level Research Centers | - |
顯示於: | 電信工程學研究所 |
在 IR 系統中的文件,除了特別指名其著作權條款之外,均受到著作權保護,並且保留所有的權利。