https://scholars.lib.ntu.edu.tw/handle/123456789/559308
標題: | Time-division multiplexing based system-level FPGA routing for logic verification | 作者: | Zou, P. Lin, Z. Shi, X. Wu, Y. Chen, J. Yu, J. YAO-WEN CHANG |
關鍵字: | Hardware Electronic design automation; Logic Verification; Multi-FPGA; Physical Design; Steiner Minimum Tree | 公開日期: | 2020 | 卷: | 2020-July | 來源出版物: | Proceedings - Design Automation Conference | 摘要: | Multi-FPGA prototyping is widely used for modern VLSI verification, but the limited number of inter-FPGA connections in a multi-FPGA system may cause routing failures. As a result, the time-division multiplexing (TDM) technique is adopted to increase its resource utilization by transmitting multiple signals through the same routing channel. Due to the large signal delay between FPGA pairs, however, the performance of such a system greatly depends on the inter-FPGA routing quality. In this paper, we propose a TDM-based system-level routing algorithm to simultaneously minimize the maximum TDM (signal multiplexing) ratio and runtime, considering the crucial ratio constraints. By weighting the routing edges, we first model the net routing as a Steiner minimum tree (SMT) problem and solve it with an approximation algorithm with the performance bound 2(1 - 1/1), where l is the number of leaves in an optimal SMT. Then, a timing-driven assignment method is presented to evenly distribute the TDM ratio to routing signals, followed by a novel reassignment algorithm to efficiently handle unbalanced net groups. Finally, a ratio-aware refinement technique is employed to further improve the solution quality. Compared with the top-3 winners at the 2019 CAD Contest at ICCAD based on the contest benchmarks, experiment results show that our proposed algorithm achieves the best runtime and TDM ratio while satisfying all TDM constraints. © 2020 IEEE. |
URI: | https://www.scopus.com/inward/record.url?eid=2-s2.0-85093961440&partnerID=40&md5=6b1d11bfdba7d323aac18c6aee891849 https://scholars.lib.ntu.edu.tw/handle/123456789/559308 |
ISSN: | 0738100X | DOI: | 10.1109/DAC18072.2020.9218569 | SDG/關鍵字: | Approximation algorithms; Computer aided design; Field programmable gate arrays (FPGA); Trees (mathematics); Logic verification; Multi-FPGA system; Performance bounds; Refinement techniques; Resource utilizations; Signal multiplexing; Solution quality; Steiner minimum trees; Time division multiplexing |
顯示於: | 電信工程學研究所 |
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