https://scholars.lib.ntu.edu.tw/handle/123456789/573497
標題: | Realistic fault models and fault simulation for quantum dot quantum circuits | 作者: | Hsieh C.-Y. Wu C.-H. Huang C.-H. Goan H.-S. Mo Li J.C. JENG-WEI CHEN |
關鍵字: | Computer aided design; Nanocrystals; Testing; Timing circuits; Confidence levels; Control errors; Fault simulation; Missing gate faults; Physical phenomena; Quantum circuit; Quantum dot devices; Sparse matrices; Semiconductor quantum dots | 公開日期: | 2020 | 卷: | 2020-July | 來源出版物: | Proceedings - Design Automation Conference | 摘要: | Testing for quantum circuits (QC) is a challenging task because QC is intrinsically probabilistic. Existing fault models for QC, such as missing gate faults, are not suitable for quantum dot QC. This paper proposes realistic fault models and fault simulation for quantum dot QC. Our fault models are based on real physical phenomenon of quantum dot devices so that they represent real defect behavior or control errors. Our fault simulation does not need to fully expand gate matrices to 2n x 2n, where n is the number of qubits. Using sparse matrix multiplication, our fault simulation saves a lot of memory and CPU time. We also calculate the test repetition of each test pattern so that we can estimate our test time. Based on fault simulation of a full adder QC, we can select a small test set of six test patterns, totally 526 repetitions, to detect all faults with 99% confidence level. ? 2020 IEEE. |
URI: | https://www.scopus.com/inward/record.uri?eid=2-s2.0-85093976057&doi=10.1109%2fDAC18072.2020.9218573&partnerID=40&md5=96616a947c172bb9fbe213843e57902b https://scholars.lib.ntu.edu.tw/handle/123456789/573497 |
ISSN: | 0738100X | DOI: | 10.1109/DAC18072.2020.9218573 |
顯示於: | 物理學系 |
在 IR 系統中的文件,除了特別指名其著作權條款之外,均受到著作權保護,並且保留所有的權利。