https://scholars.lib.ntu.edu.tw/handle/123456789/580703
標題: | Hardware implementation of physically unclonable function (puf) in perpendicular STT MRAM | 作者: | CHIH-I WU | 關鍵字: | Hamming distance; Hardware; VLSI circuits; CMOS processs; Cost effective; Fully integrated; Hamming weights; Hardware implementations; Physically unclonable functions; Security electronics; Wafer processing; Magnetic recording | 公開日期: | 2017 | 來源出版物: | 2017 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2017 | 摘要: | The pSTT MRAM array with stepped structure MTJ is fully integrated with standard 0.18 μm CMOS process. Using a low power etch process greatly improves the uniformity of MR and RP. The bit pattern is randomized with a voltage method and a cost-effective field method; the latter can be incorporated into wafer processing. We showed the bit pattern is unpredictable under the same sub-critical stimulation, thus, practically unclonable. The Hamming Weight and inter-chip Hamming Distance are both ?50%, an evidence of sufficient uniqueness. A single embedded STT-MRAM PUF can cover many needs of security electronics. ? 2017 IEEE. |
URI: | https://www.scopus.com/inward/record.uri?eid=2-s2.0-85023168400&doi=10.1109%2fVLSI-TSA.2017.7942497&partnerID=40&md5=2ca50fc540704da4808dfd84c57a66f5 https://scholars.lib.ntu.edu.tw/handle/123456789/580703 |
DOI: | 10.1109/VLSI-TSA.2017.7942497 |
顯示於: | 電機工程學系 |
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