https://scholars.lib.ntu.edu.tw/handle/123456789/580769
標題: | Intelligent Design Automation for 2.5/3D Heterogeneous SoC Integration | 作者: | Jiang I.H.-R Chang Y.-W Huang J.-L CHUNG-PING CHEN HUI-RU JIANG JIUN-LANG HUANG YAO-WEN CHANG |
關鍵字: | Chip scale packages; Computer aided design; Costs; Indium compounds; Integration; Integration testing; Printed circuit design; Programmable logic controllers; System-on-chip; Co-design methodology; Design complexity; Electrical effects; Heterogeneous integration; Intelligent designs; Low-cost packaging; Package on packages; SOC integration; Integrated circuit design | 公開日期: | 2020 | 卷: | 2020-November | 來源出版物: | IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD | 摘要: | As the design complexity grows dramatically in modern circuit designs, 2.5D/3D chip/package/board integration has become a key to beat process limitation for optimizing system performance and power consumption. Among the explored technologies, the wafer-level integrated fan-out (InFO) package-on-package (PoP) has been adopted by major companies such as TSMC to achieve high-density, high-performance, low-cost packaging solutions. To achieve a high-quality 2.5D/3D heterogeneous integration system, we shall study the chip, package, and board codesign methodology with advanced packages and explore key techniques to handle the emerging challenges in physical design, timing, electrical effects, and testing. ? 2020 Association on Computer Machinery. |
URI: | https://www.scopus.com/inward/record.uri?eid=2-s2.0-85097955684&doi=10.1145%2f3400302.3415767&partnerID=40&md5=552cbb8be2bed3d3a8dac18d666d6ed4 https://scholars.lib.ntu.edu.tw/handle/123456789/580769 |
ISSN: | 10923152 | DOI: | 10.1145/3400302.3415767 |
顯示於: | 電機工程學系 |
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