https://scholars.lib.ntu.edu.tw/handle/123456789/580852
標題: | A 34.3?dB SNDR, 2.3GS/s, Sub-radix pipeline ADC using incomplete settling technique with background radix detector | 作者: | Chen H.-S Tseng C.-J Chen C.-M Chen H.-W. HSIN-SHU CHEN |
關鍵字: | Operational amplifiers; Pipelines; CMOS processs; Conversion rates; Input frequency; Low-bandwidth; Pipeline ADCs; Simulated results; Single channels; Stage gains; Analog to digital conversion | 公開日期: | 2021 | 卷: | 107 | 期: | 1 | 起(迄)頁: | 39-50 | 來源出版物: | Analog Integrated Circuits and Signal Processing | 摘要: | A 6-bit 2.3 GS/s single-channel sub-radix pipeline ADC using an incomplete settling concept is presented. A radix detector is proposed to detect stage gain in the background so that low gain and low bandwidth opamps can be utilized to conserve power. The raw ADC output codes can be reconstructed with the detected radix to retrieve its accuracy. The simulated results show that the prototype ADC in 40?nm CMOS process exhibits an SNDR of 34.3?dB at Nyquist input frequency with the conversion rate of 2.3 GS/s. It consumes 94 mW at 1?V supply and occupies an active chip area of 0.12?mm2. ? 2021, The Author(s), under exclusive licence to Springer Science+Business Media, LLC, part of Springer Nature. |
URI: | https://www.scopus.com/inward/record.uri?eid=2-s2.0-85102344130&doi=10.1007%2fs10470-021-01814-1&partnerID=40&md5=b1dbbdaa7a7fcb99ecd3ff959597c402 https://scholars.lib.ntu.edu.tw/handle/123456789/580852 |
ISSN: | 09251030 | DOI: | 10.1007/s10470-021-01814-1 |
顯示於: | 電機工程學系 |
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