|Title:||3D integration of vertical-stacking of MoS2and Si CMOS featuring embedded 2T1R configuration demonstrated on full wafers||Authors:||Su, Chunjung
Lee, K. S.
VITA PI-HO HU
Huang, Y. F.
Zheng, B. C.
Yao, C. H.
Kao, Kuo-Hsing Hsing
Hong, Tzu Chieh
Tseng, Y. C.
Lin, C. L.
|Keywords:||Computation theory; Electron devices; Embedded systems; Layered semiconductors; Molybdenum compounds; RRAM; Silicon wafers; Three dimensional integrated circuits; 3-D integration; CMOS inverters; Compatible process; Computing system; Multiple channels; Performance matching; Resistive switching; Vertical stacking; CMOS integrated circuits||Issue Date:||2020||Journal Volume:||2020-December||Start page/Pages:||12.2.1 - 12.2.4||Source:||Technical Digest - International Electron Devices Meeting, IEDM||Conference:||66th Annual IEEE International Electron Devices Meeting, IEDM 2020||Abstract:||
For the first time, a 3D stacking of MoS2 and Si CMOS integrated with embedded RRAM is proposed and fabricated, and CMOS inverter comprised of MoS2 nFET and Si pFET is demonstrated. Vertically stacked multiple MoS2 channels are required for the performance matching. Resistive switching (RS) of a Ti/MoS2 /p+-Si structure showing high ON/OFF ratio of 106 is demonstrated firstly by highly Si-compatible process. Surface modification is the key to formation of uniform and smooth stacked MoS2 multiple channels and to enhanced resistive switching endurance. This scheme can be applied to CMOS-based bipolar RRAM 1T1R or 2T1R without increasing the cell size. Our work offers a new pathway with high feasibility of integrated 2D materials and Si FETs into CMOS to enabling 3D embedded logics and memories for future computing systems. ? 2020 IEEE.
|Appears in Collections:||電機工程學系|
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.