https://scholars.lib.ntu.edu.tw/handle/123456789/581139| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Lu Y.-R | en_US |
| dc.contributor.author | SHEN-IUAN LIU | en_US |
| dc.contributor.author | Yang Y.-C | en_US |
| dc.contributor.author | Kang H.-C | en_US |
| dc.contributor.author | Chen C.-L | en_US |
| dc.contributor.author | Chan K.-U | en_US |
| dc.contributor.author | Lin Y.-H. | en_US |
| dc.creator | Lu Y.-R;Liu S.-I;Yang Y.-C;Kang H.-C;Chen C.-L;Chan K.-U;Lin Y.-H. | - |
| dc.date.accessioned | 2021-09-02T00:07:30Z | - |
| dc.date.available | 2021-09-02T00:07:30Z | - |
| dc.date.issued | 2021 | - |
| dc.identifier.issn | 15497747 | - |
| dc.identifier.uri | https://www.scopus.com/inward/record.uri?eid=2-s2.0-85101967322&doi=10.1109%2fTCSII.2020.3022833&partnerID=40&md5=19f029c99d994b5876e4324463ef2b6e | - |
| dc.identifier.uri | https://scholars.lib.ntu.edu.tw/handle/123456789/581139 | - |
| dc.description.abstract | A sub-sampling phase-locked loop (SSPLL) with loop bandwidth calibration is presented. By using a sub-sampling phase detector with gain calibration and a pulse width control circuit, the loop bandwidth deviation of the SSPLL can be reduced. This SSPLL is fabricated in a 40 nm CMOS process and its core area is 0.15mm2. The power consumption of the SSPLL is 5.81mW from a supply of 1.1V. The reference frequency is 75 MHz and the output frequency range of the SSPLL is 2.43.0GHz. The measured rms jitter is 2.02ps at the output frequency of 3.0GHz. With the calibration, the largest loop bandwidth deviation from 3.5MHz among five samples is reduced from-71.4% to-18.5% at 3.0GHz. ? 2004-2012 IEEE. | - |
| dc.relation.ispartof | IEEE Transactions on Circuits and Systems II: Express Briefs | - |
| dc.subject | Loop bandwidth calibration; phase-locked loop; pulse width; slew rate; sub-sampling phase detector | - |
| dc.subject.other | Bandwidth; Calibration; Phase comparators; CMOS processs; Gain calibration; Loop bandwidth; Output frequency; Process tolerant; Pulse width control; Reference frequency; Sub-sampling; Phase locked loops | - |
| dc.title | A 2.4-3.0GHz Process-Tolerant Sub-Sampling PLL with Loop Bandwidth Calibration | en_US |
| dc.type | journal article | - |
| dc.identifier.doi | 10.1109/TCSII.2020.3022833 | - |
| dc.identifier.scopus | 2-s2.0-85101967322 | - |
| dc.relation.pages | 873-877 | - |
| dc.relation.journalvolume | 68 | - |
| dc.relation.journalissue | 3 | - |
| item.openairetype | journal article | - |
| item.fulltext | no fulltext | - |
| item.grantfulltext | none | - |
| item.openairecristype | http://purl.org/coar/resource_type/c_6501 | - |
| item.cerifentitytype | Publications | - |
| crisitem.author.dept | Electrical Engineering | - |
| crisitem.author.dept | Electronics Engineering | - |
| crisitem.author.dept | MediaTek-NTU Research Center | - |
| crisitem.author.orcid | 0000-0002-3765-2948 | - |
| crisitem.author.parentorg | College of Electrical Engineering and Computer Science | - |
| crisitem.author.parentorg | College of Electrical Engineering and Computer Science | - |
| crisitem.author.parentorg | Others: University-Level Research Centers | - |
| Appears in Collections: | 電機工程學系 | |
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