| Issue Date | Title | Author(s) | Source | scopus | WOS | Fulltext/Archive link |
| 2007 | 10GBase-T乙太網路系統晶片設計－子計畫五：適用於10GBase-T乙太網路之高效能數位信號處理引擎設計(3/3) | 吳安宇 | | | | |
| 2007 | 10GBase-T乙太網路系統晶片設計－子計畫四：適用於10GBase-T乙太網路接收機之類比數位轉換電路(2/3) | 劉深淵 | | | | |
| 2007 | 10GBase-T乙太網路系統晶片設計－子計畫四：適用於10GBase-T乙太網路接收機之類比數位轉換電路(3/3) | 劉深淵 | | | | |
| 2008 | 10GBase-T乙太網路系統晶片設計－總計畫(2/3) | 劉深淵 | | | | |
| 2007 | 10GBase-T乙太網路系統晶片設計－總計畫(3/3) | 劉深淵 | | | | |
| 2005 | 10位元 250MSample/s 內插式數位類比轉換器 | 郭漢松; Kuo, Han-Sung | | | |  |
| 2016 | A 12-bit 210-MS/s 2-Times Interleaved Pipelined-SAR ADC With a Passive Residue Transfer Technique | C-Y Lin; T-C Lee; TAI-CHENG LEE | IEEE Transactions on Circuits and Systems, Part I | 24 | 22 | |
| 0 | A 12-bit 600-MS/s time-interleaved SAR ADC with background timing skew calibration | 5. Y-H Wei; C-Y Lin; T-C Lee; TAI-CHENG LEE | IEEE International Symposium on Radio-Frequency Integration Technology (RFIT) | 13 | 0 | |
| 2006 | 124Ms/s pixel-pipelined motion-JPEG 2000 codec without tile memory | Chang, Yu-Wei; Fang, Hung-Chi; Cheng, Chih-Chi; Chen, Chun-Chia; Lian, Chung-Jr; Chien, Shao-Yi ; Chen, Liang-Gee | IEEE International Solid-State Circuits Conference | 0 | 0 | |
| 2015 | A 127 fJ/Conv. Continuous-Time Delta-Sigma Modulator with a DWA-Embedded Two-Step Time-Domain Quantizer | C.-H. Weng; T.-A. Wei; T.-H. Lin; TSUNG-HSIEN LIN ; 林宗賢 | IEEE VLSI-DAT | 0 | 0 | |
| 2015 | A 13-MHz 68-dB SNDR CTDSM Using SAB Loop Filter and Interpolating Flash Quantizer with Random-Skip IDWA Function in 90-nm CMOS | C.-H. Weng; W.-H. Huang; E. Alpman; T.-H. Lin; TSUNG-HSIEN LIN ; 林宗賢 | IEEE A-SSCC | 2 | 0 | |
| 2016 | A 13.56-MHz Passive NFC Tag IC in 0.18-μm CMOS Process for Biomedical Applications | C.-H. Lu; J.-A. Li; T.-H. Lin; TSUNG-HSIEN LIN ; 林宗賢 | IEEE VLSI-DAT | 8 | 0 | |
| 2014 | A 135 uW 0.46mOhm/rtHz Thoracic Impedance Variance Monitor with Square-Wave Current Modulation | C.-C. Tu; F. -Y. Lee; T. -H. Lin; TSUNG-HSIEN LIN ; 林宗賢 | IEEE A-SSCC | | | |
| 2015 | A 2-channel ?83.2dB crosstalk 0.061mm2 CCIA with an orthogonal frequency chopping technique | Y. -L. Tsai; F. -W. Lee; T. -Y. Chen; T. -H. Lin; TSUNG-HSIEN LIN ; 林宗賢 | IEEE ISSCC | | | |
| 2000 | A 2-V 10.7MHz CMOS Limiting Amplifier/RSSI | Huang, Po-Chiun; Chen, Yi-Huei; 汪重光; Chen, Yi-Huei; Wang, Chorng-Kuang | Proceedings of the 11th VLSI/CAD Symposium | | | |
| 2000 | A 2-V 10.7MHz CMOS Limiting Amplifier/RSSI | Huang, Po-Chiun; Chen, Yi-Huei; 汪重光; Chen, Yi-Huei; Wang, Chorng-Kuang | IEEE Journal of Solid-state Circuits | | | |
| 1999 | A 2-V 7.2?a Jitter AM-Suppression CMOS Amplifier using Current-Mode Hybrid Magnitude Control | Huang, Kuang-Hu; Wang, Wei-Cheng; Yang, Tang-Huei; 汪重光; Wang, Wei-Cheng; Wang, Chorng-Kuang | IEEE Journal of Solid-state Circuits | | | |
| 2001 | A 2-V CMOS 455KHz FM/FSK Demodulator using Feedforward Offset Cancellation Limiting Amplifier | Huang, Po-Chiun; Chen, Yi-Huei; 汪重光; Huang, Po-Chiun; Chen, Yi-Huei; Wang, Chorng-Kuang | IEEE Journal of Solid-state Circuits | | | |
| 1999 | A 2.4 GHz CMOS Low-IF Receiver | Yi Lu; Huang, Kuang-Hu; 汪重光; Wang, C. K. | International Analog VLSI Workshop, Taipei, Taiwan(1999.05) | | | |
| 2009 | 2.4 GHz low-pass filters with harmonic suppression using integrated passive device process | Wu, J.-K.; Pan, C.; Chiang, C.-W.; Fu, H.-C.; HSIN-CHIA LU | 2009 International Symposium on VLSI Design, Automation and Test | 3 | 0 | |
