https://scholars.lib.ntu.edu.tw/handle/123456789/607290
標題: | A Low-Jitter Sub-Sampling PLL With a Sub-Sampling DLL | 作者: | Qian Y.C Chao Y.Y SHEN-IUAN LIU |
關鍵字: | Capacitors;Clocks;Delays;Phase locked loops;Phase noise;Voltage control;Voltage-controlled oscillators;Jitter;Delay-locked loops;In-band phase noise;Loop bandwidth;Offset frequencies;Output frequency;Reference clock;Reference spur;Root mean square jitter;Delay lock loops | 公開日期: | 2022 | 卷: | 69 | 期: | 2 | 起(迄)頁: | 269-273 | 來源出版物: | IEEE Transactions on Circuits and Systems II: Express Briefs | 摘要: | A sub-sampling phase-locked loop (SSPLL) with a sub-sampling delay-locked loop is presented to extend the loop bandwidth and achieve the low jitter. A falling-edge tuning loop is added to align the falling edge of the reference clock with the rising one of the output clock. The proposed SSPLL is realized in a 0.18μm CMOS process and its active area is 0.185mm2. At the output frequency of 2.2GHz, the proposed SSPLL achieves an in-band phase noise of -111.83dBc/Hz and -116.41dBc/Hz at 100kHz and 4MHz offset frequency respectively with a division ratio of 44. Its root-mean-square jitter integrated from 10kHz to 100MHz is 655fs. The measured reference spur is -50.3dBc. ? 2021 IEEE. |
URI: | https://www.scopus.com/inward/record.uri?eid=2-s2.0-85113222044&doi=10.1109%2fTCSII.2021.3105552&partnerID=40&md5=2b31844e10e95cb1639f61af78d9322e https://scholars.lib.ntu.edu.tw/handle/123456789/607290 |
ISSN: | 15497747 | DOI: | 10.1109/TCSII.2021.3105552 |
顯示於: | 電機工程學系 |
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