https://scholars.lib.ntu.edu.tw/handle/123456789/607292
標題: | An Adaptive Loop Gain Tracking Digital PLL Using Spectrum-Balancing Technique | 作者: | Su G.-Y Kang Z.-H SHEN-IUAN LIU |
關鍵字: | adaptive loop gain controller;and phase noise;bang-bang phase-frequency detector;digital phase-locked loop;jitter;spectrum-balancing technique;Phase comparators;VLSI circuits;Adaptive loops;Balancing techniques;CMOS processs;Digital phase locked loops;High frequency HF;Phase frequency detectors;Root mean square jitter;Supply voltages;Phase locked loops | 公開日期: | 2021 | 來源出版物: | 2021 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2021 - Proceedings | 摘要: | A digital phase-locked loop (DPLL) using the proposed adaptive loop gain controller (ALGC) is presented. The ALGC uses a spectrum-balancing technique to detect the difference of the high-frequency and the low-frequency powers of the bang-bang phase-frequency detector output. Then, the loop gain of the DPLL is adjusted to minimize the output root-mean-square (RMS) jitter. This DPLL is fabricated in 40-nm CMOS process and its active area is 0.016mm2. Operating at a frequency of 3.2 GHz, the power consumption of the DPLL is 1.5mW from a 1V supply voltage. ? 2021 IEEE. |
URI: | https://www.scopus.com/inward/record.uri?eid=2-s2.0-85106643711&doi=10.1109%2fVLSI-DAT52063.2021.9427319&partnerID=40&md5=45ec9f77e6fcaa4b0be5ca581906fdcd https://scholars.lib.ntu.edu.tw/handle/123456789/607292 |
DOI: | 10.1109/VLSI-DAT52063.2021.9427319 |
顯示於: | 電機工程學系 |
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