https://scholars.lib.ntu.edu.tw/handle/123456789/607315
標題: | A Single-Channel 1-GS/s 7.48-ENOB Parallel Conversion Pipelined SAR ADC with a Varactor-Based Residue Amplifier | 作者: | Chang H Lin T TAI-CHENG LEE |
關鍵字: | Analog-digital conversion;Capacitance;Dynamic Amplifier;Linearity;Parallel Conversion;Pipelined SAR ADC;Registers;Single Channel;Switches;Varactor-Based Compensation.;Varactors;Voltage;Analog to digital conversion;Dynamic amplifier;Parallel conversion;Register;Residue conversion;SAR ADC;Single channels;Varactor-based compensation. | 公開日期: | 2022 | 來源出版物: | IEEE Transactions on Circuits and Systems II: Express Briefs | 摘要: | A pipelined SAR ADC is proposed to achieve faster conversion by employing residue conversion and partial bit conversion in parallel to lessen timing constraints. Additionally, a varactor-based dynamic amplifier is adopted to improve linearity for a 10-b accuracy. The single-channel ADC achieves 1 GS/s with a peak SNDR 41.37 dB at a Nyquist input and consumes 9.4 mW. IEEE |
URI: | https://www.scopus.com/inward/record.uri?eid=2-s2.0-85123366248&doi=10.1109%2fTCSII.2022.3142099&partnerID=40&md5=928d381cfc88138d4f100079735d1dc1 https://scholars.lib.ntu.edu.tw/handle/123456789/607315 |
ISSN: | 15497747 | DOI: | 10.1109/TCSII.2022.3142099 |
顯示於: | 電機工程學系 |
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