https://scholars.lib.ntu.edu.tw/handle/123456789/607516
標題: | VLSI Structure-aware Placement for Convolutional Neural Network Accelerator Units | 作者: | Chou Y Hsu J.-W Chen T.-C. YAO-WEN CHANG |
關鍵字: | Convolutional neural networks;Multilayer neural networks;Traffic congestion;VLSI circuits;AI applications;Circuit structures;Complicated structures;Convolutional neural network;Dedicated hardware;Hardware design;Neural-networks;Routing congestion;Structure-aware;VLSI structures;Convolution | 公開日期: | 2021 | 卷: | 2021-December | 起(迄)頁: | 1117-1122 | 來源出版物: | Proceedings - Design Automation Conference | 摘要: | AI-dedicated hardware designs are growing dramatically for various AI applications. These designs often contain highly connected circuit structures, reflecting the complicated structure in neural networks, such as convolutional layers and fully-connected layers. As a result, such dense interconnections incur severe congestion problems in physical design that cannot be solved by conventional placement methods. This paper proposes a novel placement framework for CNN accelerator units, which extracts kernels from the circuit and insert kernel-based regions to guide placement and minimize routing congestion. Experimental results show that our framework effectively reduces global routing congestion without wirelength degradation, significantly outperforming leading commercial tools. ? 2021 IEEE. |
URI: | https://www.scopus.com/inward/record.uri?eid=2-s2.0-85119423062&doi=10.1109%2fDAC18074.2021.9586294&partnerID=40&md5=85997d79c34585e55c89b3b51f5f01e5 https://scholars.lib.ntu.edu.tw/handle/123456789/607516 |
ISSN: | 0738100X | DOI: | 10.1109/DAC18074.2021.9586294 |
顯示於: | 電信工程學研究所 |
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