https://scholars.lib.ntu.edu.tw/handle/123456789/632233
標題: | D-NAT: Data-Driven Non-Ideality Aware Training Framework for Fabricated Computing-In-Memory Macros | 作者: | Lin M.-G Huang C.-T Chuang Y.-C Chen Y.-T Hsu Y.-T Chen Y.-K Chou J.-J TSUNG-TE LIU CHI-SHENG SHIH AN-YEU(ANDY) WU |
關鍵字: | Computing-in-memory (CIM); deep neural network (DNN); non-ideality aware training | 公開日期: | 2022 | 卷: | 12 | 期: | 2 | 起(迄)頁: | 381-392 | 來源出版物: | IEEE Journal on Emerging and Selected Topics in Circuits and Systems | 摘要: | To enable energy-efficient computation for deep neural networks (DNNs) at edge, computing-in-memory (CIM) is proposed to reduce the energy costs during intense off-chip memory access. However, CIM is prone to multiply-accumulate (MAC) errors due to non-idealities of memory crossbars and peripheral circuits, which severely degrade the accuracy of DNNs. In this work, we propose a Data-Driven Non-ideality Aware Training (D-NAT) framework to compensate for the accuracy degradation. The proposed D-NAT framework has the following contributions: 1) We measured a fabricated SRAM-based CIM macro to obtain a data-driven MAC error model (D-MAC-EM). Based on the derived D-MAC-EM, we analyze the impact of the non-idealities on DNN's accuracy. 2) To make DNNs robust to the non-idealities of CIM macros, we incorporate the measured D-MAC-EM into DNN's training procedure. Moreover, we propose a statistical training mechanism to better estimate the gradients of the discrete D-MAC-EM. 3) We investigate trade-offs between quantization range and quantization errors. To mitigate the quantization errors in activations, we introduce extended PACT (E-PACT) that adaptively learns the upper and lower bounds of input activations for each layer. Simulation results show that our proposed D-NAT improves the accuracy of ResNet20, VGG8, ResNet34, and VGG16 by 78.98%, 71.8%, 72.04%, and 57.85%, respectively, which reaches the ideal upper bound of the quantized model. Lastly, the D-NAT framework is validated on an FPGA platform with the fabricated SRAM-based CIM macro chip. Based on the measurement results, D-NAT successfully recovers the accuracy under non-idealities of a real SRAM-based CIM macro. © 2011 IEEE. |
URI: | https://www.scopus.com/inward/record.uri?eid=2-s2.0-85129374546&doi=10.1109%2fJETCAS.2022.3171268&partnerID=40&md5=eb0315c5c9a4bc027585b3c6862cc815 https://scholars.lib.ntu.edu.tw/handle/123456789/632233 |
ISSN: | 21563357 | DOI: | 10.1109/JETCAS.2022.3171268 | SDG/關鍵字: | Chemical activation; Deep neural networks; Economic and social effects; Energy efficiency; Errors; Static random access storage; Timing circuits; Circuits and systems; Common information model (computing); Computational modelling; Computing-in-memory; Deep neural network; Hardware; Information Modeling; Non-ideality aware training; Nonideality; Quantization (signal); Semiconductor device measurements; Quantization (signal) |
顯示於: | 資訊工程學系 |
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