https://scholars.lib.ntu.edu.tw/handle/123456789/633930
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Huang, Jing-Kai | en_US |
dc.contributor.author | Wan, Yi | en_US |
dc.contributor.author | Shi, Junjie | en_US |
dc.contributor.author | Zhang, Ji | en_US |
dc.contributor.author | Wang, Zeheng | en_US |
dc.contributor.author | Wang, Wenxuan | en_US |
dc.contributor.author | Yang, Ni | en_US |
dc.contributor.author | Liu, Yang | en_US |
dc.contributor.author | Lin, Chun-Ho | en_US |
dc.contributor.author | Guan, Xinwei | en_US |
dc.contributor.author | Hu, Long | en_US |
dc.contributor.author | Yang, Zi-Liang | en_US |
dc.contributor.author | Huang, Bo-Chao | en_US |
dc.contributor.author | YA-PING CHIU | en_US |
dc.contributor.author | Yang, Jack | en_US |
dc.contributor.author | Tung, Vincent | en_US |
dc.contributor.author | Wang, Danyang | en_US |
dc.contributor.author | Kalantar-Zadeh, Kourosh | en_US |
dc.contributor.author | Wu, Tom | en_US |
dc.contributor.author | Zu, Xiaotao | en_US |
dc.contributor.author | Qiao, Liang | en_US |
dc.contributor.author | Li, Lain-Jong | en_US |
dc.contributor.author | Li, Sean | en_US |
dc.date.accessioned | 2023-07-18T06:48:47Z | - |
dc.date.available | 2023-07-18T06:48:47Z | - |
dc.date.issued | 2022-05 | - |
dc.identifier.issn | 00280836 | - |
dc.identifier.uri | https://scholars.lib.ntu.edu.tw/handle/123456789/633930 | - |
dc.description.abstract | The scaling of silicon metal-oxide-semiconductor field-effect transistors has followed Moore's law for decades, but the physical thinning of silicon at sub-ten-nanometre technology nodes introduces issues such as leakage currents1. Two-dimensional (2D) layered semiconductors, with an atomic thickness that allows superior gate-field penetration, are of interest as channel materials for future transistors2,3. However, the integration of high-dielectric-constant (κ) materials with 2D materials, while scaling their capacitance equivalent thickness (CET), has proved challenging. Here we explore transferrable ultrahigh-κ single-crystalline perovskite strontium-titanium-oxide membranes as a gate dielectric for 2D field-effect transistors. Our perovskite membranes exhibit a desirable sub-one-nanometre CET with a low leakage current (less than 10-2 amperes per square centimetre at 2.5 megavolts per centimetre). We find that the van der Waals gap between strontium-titanium-oxide dielectrics and 2D semiconductors mitigates the unfavourable fringing-induced barrier-lowering effect resulting from the use of ultrahigh-κ dielectrics4. Typical short-channel transistors made of scalable molybdenum-disulfide films by chemical vapour deposition and strontium-titanium-oxide dielectrics exhibit steep subthreshold swings down to about 70 millivolts per decade and on/off current ratios up to 107, which matches the low-power specifications suggested by the latest International Roadmap for Devices and Systems5. | en_US |
dc.language.iso | en | en_US |
dc.relation.ispartof | Nature | en_US |
dc.title | High-κ perovskite membranes as insulators for two-dimensional transistors | en_US |
dc.type | journal article | en |
dc.identifier.doi | 10.1038/s41586-022-04588-2 | - |
dc.identifier.pmid | 35546188 | - |
dc.identifier.scopus | 2-s2.0-85130633806 | - |
dc.identifier.url | https://api.elsevier.com/content/abstract/scopus_id/85130633806 | - |
dc.relation.journalvolume | 605 | en_US |
dc.relation.journalissue | 7909 | en_US |
dc.relation.pageend | 267 | en_US |
item.fulltext | no fulltext | - |
item.languageiso639-1 | en | - |
item.openairecristype | http://purl.org/coar/resource_type/c_6501 | - |
item.cerifentitytype | Publications | - |
item.openairetype | journal article | - |
item.grantfulltext | none | - |
crisitem.author.dept | Applied Physics | - |
crisitem.author.dept | Program in Nanoengineering and Nanoscience | - |
crisitem.author.orcid | 0000-0001-7065-4411 | - |
crisitem.author.parentorg | College of Science | - |
crisitem.author.parentorg | Graduate School of Advanced Technology | - |
顯示於: | 物理學系 |
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