https://scholars.lib.ntu.edu.tw/handle/123456789/634794
標題: | 4-Layer Wafer on Wafer Stacking Demonstration with Face to Face/Face to Back Stacked Flexibility Using Hybrid Bond/TSV-Middle for Various 3D Integration | 作者: | Lu, C. L. Chuang, C. H. Huang, C. H. Lin, S. C. Chang, Y. H. Lai, W. Y. Chiu, M. H. MING-HAN LIAO Chang, S. Z. |
公開日期: | 1-一月-2023 | 卷: | 2023-June | 來源出版物: | Digest of Technical Papers - Symposium on VLSI Technology | 摘要: | Different from Chip on Wafer stacking technology, Wafer on Wafer (WoW) stacking can provide a tighter pitch and higher interconnect density with higher through-put. The difficulty for WoW stacking is on wafer surface and edge treatment. In this work, a 4-layer WoW stacking architecture on 12 -inch wafers with hybrid bonding/bump-less and through-silicon-via (TSV) middle techniques for enabling various 3D integration has been demonstrated and proposed. It projects > 15 % form factor and > 10 % interconnection resistance reduction than typical scheme. Low process temperature (180°C-250°C) is implemented for whole stacking process. Depending on different applications, both of wafers by Face to Face (F2F) and Face to Back (F2B) stacking processes are developed. For bump-less HBM-like structure, it needs special temporary bond and de-pond process for F2B bonding. F2F bonding can present a high dense interconnection for logic to memory AI computing application. The results of 4 layers (TSV x 3 and hybrid bond interface x 3) show that interconnection resistance is < 0.25 Ω per loop. It contains 17Kea of TSVs (5 E 3 / mm2) and 230Kea of hybrid bond pads (2 E 5 / mm2). From the eye-diagram and insertion loss simulation, hybrid bond/bump-less scheme leads to ∼ 40 % performance improvement than it in the bump scheme. |
URI: | https://scholars.lib.ntu.edu.tw/handle/123456789/634794 | ISBN: | 9784863488069 | ISSN: | 07431562 | DOI: | 10.23919/VLSITechnologyandCir57934.2023.10185308 |
顯示於: | 機械工程學系 |
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