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Issue Date	Title	Author(s)	Source	scopus	WOS
2009	0.5V SOI CMOS Dual-Threshold Circuit Technique Via DTMOS for Design Optimization of Low-Power VLSI System Applications	W. J. H. Lin; C. Y. Chien; J. B. Kuo; JAMES-B KUO	EUROSOI
2005	0.7 V Manchester carry look-ahead circuit using PD SOI CMOS asymmetrical dynamic threshold pass transistor techniques suitable for low-voltage CMOS VLSI systems	T. Y. Chiang; JAMES-B KUO	IEE Proceddings on Circuits, Devices and Systems	2	2
2002	0.8 V CMOS adiabatic differential switch logic circuit using bootstrap technique for low-voltage low-power VLSI	Z. Zhang; H. H. Chen; J. B. Kuo; JAMES-B KUO	Electronics Letters	22	16
2002	0.8V CMOS Content-Addressable-Memory (CAM) Cell Ciurcuit with a Fast Tag-Compare Capability Using Bulk PMOS Dynamic-Threshold (BP-DTMOS) Technique Based on Standard CMOS Technology for Low-Voltage VLSI Systems	E. Shen; J. B. Kuo; JAMES-B KUO	International Symposium on Circuits and Systems (ISCAS) Proceedings	0	0
1997	1.5 V CMOS full-swing energy efficient logic (EEL) circuit suitable for low-voltage and low-power VLSI applications	Yeh, C.C.; Lou, J.H.; JAMES-B KUO	ELECTRONICS LETTERS 31st July	16	13
1993	1.5V BiCMOS dynamic multiplier using Wallace tree reduction architecture	Kuo, J.B.; Su, K.W.; Lou, J.H.; KuoJB	Electronics Letters	2	0
2002	A 0.8-V 128-Kb Four-Way Set-Associative Two-Level CMOS Cache Memory Using Two-Stage Wordline/Bitline-Oriented Tag-Compare (WLOTC/BLOTC) Scheme	P. F. Lin; J. B. Kuo; JAMES-B KUO	IEEE Journal of Solid-State Circuits	18	13
2001	A 0.8V 0.77mW at 50MHz 128Kb Four-Way Set-Associative 2-Level CMOS Cache Memory Using Two-Stage WLOTC/BLOTC Tag-Compare Scheme and Sense Wordline/Bitlines (SWL/SBL) Tag Sense Amps with an 8-T Tag Cell in Level 2 and a 10-T Shrunk Logic Swing (SLS) Memory	J. B. Kuo; P. F. Lin; JAMES-B KUO	European Solid-State Circuits Conference (ESSCIRC)
2004	A 0.8V CMOS TSPC Adiabatic DCVS Logic Circuit with the Bootstrap Technique for Low-Power VLSI	H. P. Chen; JAMES-B KUO	ICECS	8	0
2001	A 1-V 128-kb four-way set-associative CMOS cache memory using wordline-oriented tag-compare (WLOTC) structure with the content-addressable-memory (CAM) 10-transistor tag cell	P. F. Lin; J. B. Kuo; JAMES-B KUO	IEEE Journal of Solid-State Circuits	44	30
1999	A 1.5-V CMOS all-N-logic true-single-phase bootstrapped dynamic-logic circuit suitable for low supply voltage and high-speed pipelined system operation	J. H. Lou; J. B. Kuo; JAMES-B KUO	IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing	4	3
1999	A 1.5V Bootstrapped All-N-Logic True-Single-Phase CMOS Dynamic Logic Circuit suitable for Low Supply Voltage and High Speed Pipelined System Operation	J. B. Kuo; J. H. Lou; JAMES-B KUO
1999	A 1.5V Bootstrapped Pass-Transistor-Based Carry Look-Ahead Circuit suitable for Low-Voltage CMOS VLSI	J. B. Kuo; J. H. Lou; JAMES-B KUO
0	A Charge-Sharing-Problem-Free 1.5V BiCMOS Dynamic Logic Gate Circuit	J. B. Kuo; JAMES-B KUO
2012	A Closed-form Analytical Transient Response Model for On-Chip Distortionless Interconnect	T. C. Liu; J. B. Kuo; S. D. Zhang; JAMES-B KUO	IEEE Transactions on Electron Devices	4	1
1999	A CMOS Semi-Static Latch Circuit without Charge Sharing and Leakage Current Problems	P. F. Lin; J. B. Kuo; JAMES-B KUO	Low-Voltage CMOS VLSI Circuits
2004	A Compact Threshold Voltage Model for Gate Misalignment Effect of DG FD SOI NMOS Devices Considering Fringing Electric Field Effects	E. C. Sun; J. B. Kuo; JAMES-B KUO	IEEE Transactions on Electron Devices	41	35
2016	A Continuous Compact Model Incorporating Higher-Order Correction for Junctionless Nanowire Tansistors with Arbitrary Doping Profiles	C Hong; L. Yang; Q. Cheng; T. Han; J. B. Kuo; Y. Chen; JAMES-B KUO	IEEE Transactions on Nanotechnology	7	5
0	A High-Speed 1.5V Clocked BiCMOS Latch for BiCMOS Dynamic Pipelined Digital Logic VLSI Systems	J. B. Kuo; J. H. Lou; JAMES-B KUO
2004	A Low-Voltage CMOS Load Driver with the Adiabatic and Bootstrap Techniques for Low-Power System Applications	J. B. Kuo; H. P. Chen; JAMES-B KUO	MWSCAS	4	0

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