公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
2003 | A Circuit SAT Solver with Signal Correlation Guided Learning | Feng Lu; Li-C. Wang; K-T. Cheng,; Ric C-Y. Huang; CHUNG-YANG HUANG | Design Automation & Test Conference | 96 | 0 | |
2009 | A False-Path Aware Formal Static Timing Analyzer Considering Simultaneous Input Transitions | Shih-Heng Tsai; Chung-Yang (Ric) Huang; CHUNG-YANG HUANG | IEEE/ACM Design Automation Conference (DAC) | 7 | | |
1998 | A New Extended Finite State Machine (EFSM) Model for RTL Design Verification | R.C.-Y. Huang; K.-T. Cheng; CHUNG-YANG HUANG | International High Level Design Validation and Test Workshop | | | |
2011 | A Robust ECO Engine by Resource-Constraint-Aware Technology Mapping and Incremental Routing Optimization | Shao-Lun Huang; Chi-An Wu; Kai-Fu Tang; Chang-Hong Hsu; CHUNG-YANG HUANG | ACM/IEEE Asia and South Pacific Design Automation Conference (ASP-DAC) | 13 | 0 | |
2010 | A Robust Functional ECO Engine by SAT Proof Minimization and Interpolation Techniques | Bo-Han Wu; Chun-Ju Yang; Chung-Yang (Ric) Huang; Jie-Hong (Rol; ) Jiang; CHUNG-YANG HUANG ; JIE-HONG JIANG | IEEE/ACM International Conference on Computer-Aided Design (ICCAD) | 36 | 0 | |
2010 | A Unified Multi-Corner Multi-Mode Static Timing Analysis Engine | Chin-Chia Nien; Shih-Heng Tsai; Chung-Yang (Ric) Huang; CHUNG-YANG HUANG | ACM/IEEE Asia and South Pacific Design Automation Conference (ASP-DAC) | 9 | 0 | |
2014 | Adaptive interpolation-based model checking | Lai, C.-Y.; Wu, C.-Y.; Huang, C.-Y.R.; CHUNG-YANG HUANG | Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC | 0 | 0 | |
2001 | An Analysis of ATPG and SAT algorithms for Formal Verification | G. Parthasarathy; K-T. Cheng; C-Y Huang; CHUNG-YANG HUANG | International High Level Design Validation and Test Workshop | 19 | 0 | |
2000 | AQUILA: An equivalence checking system for large sequential designs | Huang, S.-Y.; Cheng, K.-T.; Chen, K.-C.; Huang, C.-Y.; Brewer, F.; CHUNG-YANG HUANG | IEEE Transactions on Computers | 37 | 24 | |
2000 | Assertion checking by combined word-level ATPG and modular arithmetic constraint-solving techniques. | Huang, Chung-Yang; Cheng, Kwang-Ting; CHUNG-YANG HUANG | Proceedings of the 37th Conference on Design Automation, Los Angeles, CA, USA, June 5-9, 2000. | 35 | 0 | |
2016 | Automatic abstraction refinement of TR for PDR | Fan, K.; Yang, M.-J.; Huang, C.-Y.; CHUNG-YANG HUANG | Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC | 2 | 0 | |
2010 | Automatic Constraint Generation for Guided Random Simulation | Hu-Hsi Yeh; Chung-Yang (Ric) Huang; CHUNG-YANG HUANG | ACM/IEEE Asia and South Pacific Design Automation Conference (ASP-DAC) | 9 | 0 | |
2008 | Characterisation of Taiwanese propolis collected from different locations and seasons | Chen, Yue-Wen; Wu, Shiao-Wen; Ho, Kai-Kuang; Lin, Shih-Bin; Huang, Chung-Yang; Chen, Chia-Nan; CHUNG-YANG HUANG | Journal of the Science of Food and Agriculture | 44 | 42 | |
2021 | Compatible Equivalence Checking of X-Valued Circuits | Wang Y.-N; Luo Y.-R; Chien P.-C; Wang P.-L; Wang H.-R; Lin W.-H; JIE-HONG JIANG ; CHUNG-YANG HUANG | IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD | 0 | 0 | |
2013 | Conquering the scheduling alternative explosion problem of SystemC symbolic simulation | Chou, C.-N.; Chu, C.-K.; Huang, C.-Y.R.; CHUNG-YANG HUANG | IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD | 11 | 0 | |
2013 | A counterexample-guided interpolant generation algorithm for SAT-based model checking | Wu, C.-Y.; Wu, C.-A.; Lai, C.-Y.; Huang, C.-Y.; CHUNG-YANG HUANG | Proceedings - Design Automation Conference | 4 | 0 | |
2014 | A Counterexample-Guided Interpolant Generation Algorithm for SAT-Based Model Checking | Wu, Cheng-Yin; Wu, Chi-An; Lai, Chien-Yu; Huang, Chung-Yang R.; CHUNG-YANG HUANG | Ieee Transactions on Computer-Aided Design of Integrated Circuits and Systems | 4 | 4 | |
2009 | Electronic Design Automation: Synthesis, Verification, and Test | L-T. Wang; K-T. Cheng; Y-W. Chang; C-Y. Huang; et. al.; CHUNG-YANG HUANG | | | | |
2009 | A false-path aware formal static timing analyzer considering simultaneous input transitions. | Tsai, Shihheng; Huang, Chung-Yang; CHUNG-YANG HUANG | Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009 | 0 | 0 | |
2016 | Fast and accurate MPSoC virtual platform simulation with parallel out-of-order execution approach | Yeh, Yu-Fu; Lin, Shu-Yen; SHU-YEN LIN ; CHUNG-YANG HUANG | Journal of the Chinese Institute of Engineers | 0 | 0 | |