| Issue Date | Title | Author(s) | Source | scopus | WOS | Fulltext/Archive link |
| 2007 | 3D Video Applications and Intelligent Video Surveillance Camera and its VLSI Design | Chien, hao-Yi; Shih, Chi-Sheng ; Ku, Mong-Kai; Yang, Chia-Lin ; Chang, Yao-Wen ; Kuo, Tei-Wei ; Chen, Liang-Gee | 2007 IEEE International Conference on Multimedia and Expo, ICME 2007 | 0 | |  |
| 2007 | 3D Video Applications and Intelligent Video Surveillance Camera and its VLSI Design. | Chien, Shao-Yi; Shih, Chi-Sheng; Ku, Mong-Kai; Yang, Chia-Lin; Chang, Yao-Wen; Kuo, Tei-Wei; CHIA-LIN YANG ; CHI-SHENG SHIH ; TEI-WEI KUO ; LIANG-GEE CHEN ; YAO-WEN CHANG ; SHAO-YI CHIEN | Proceedings of the 2007 IEEE International Conference on Multimedia and Expo, ICME 2007, July 2-5, 2007, Beijing, China | 0 | 0 | |
| 2015 | A buffer cache architecture for smartphones with hybrid DRAM/PCM memory | Lin, Y.-J.; Yang, C.-L.; Li, H.-P.; Wang, C.-Y.M.; CHIA-LIN YANG | 2015 IEEE Non-Volatile Memory Systems and Applications Symposium, NVMSA 2015 | 14 | 0 | |
| 2012 | A cycle-level SIMT-GPU simulation framework | Wang, P.-H.; Lo, C.-W.; Yang, C.-L.; Cheng, Y.-J.; CHIA-LIN YANG | IEEE International Symposium on Performance Analysis of Systems and Software | 7 | 0 | |
| 2009 | A multi-core architecture based parallel framework for h.264/avc deblocking filters | Wang, Sung-Wen; Yang, Shu-Sian; Chen, Hong-Ming; Yang, Chia-Lin; Wu, Ja-Ling; JA-LING WU ; CHIA-LIN YANG | Journal of Signal Processing Systems | 16 | 13 |  |
| 2003 | A power-aware SWDR cell for reducing cache write power | Chang, Yen-Jen; Yang, Chia-Lin ; Lai, Feipei | 2003 International Symposium on Low Power Electronics and Design | 2 | 0 | |
| 2009 | A predictive shutdown technique for GPU shader processors | Wang, Po-Han; Chen, Yen-Ming; Yang, Chia-Lin; Cheng, Yu-Jung; CHIA-LIN YANG | IEEE Computer Architecture Letters | 16 | 12 | |
| 2002 | A programmable memory hierarchy for prefetching linked data structures | Yang, C.-L.; CHIA-LIN YANG ; CHIA-LIN YANG | Lecture Notes in Computer Science | 4 | 0 | |
| 2008 | A progressive-ILP based routing algorithm for cross-referencing biochips | Yuh, Ping-Hung; Sapatnekar, S.; Yang, Chia-Lin; Chang, Yao-Wen; YAO-WEN CHANG ; CHIA-LIN YANG | Design Automation Conference | 67 | 0 | |
| 2009 | A progressive-ILP-based routing algorithm for the synthesis of cross-referencing biochips | Yuh, P.-H.; Sapatnekar, S.S.; Yang, C.-L.; Chang, Y.-W.; YAO-WEN CHANG ; CHIA-LIN YANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 2 | 5 | |
| 2011 | A SAT-based routing algorithm for cross-referencing biochips | Yuh, P.-H.; Lin, C.C.-Y.; Huang, T.-W.; Ho, T.-Y.; Yang, C.-L.; Chang, Y.-W.; YAO-WEN CHANG ; CHIA-LIN YANG | International Workshop on System Level Interconnect Prediction, SLIP | 10 | 0 | |
| 2018 | Active forwarding: Eliminate IOMMU address translation for accelerator-rich architectures | Fu, H.-C.; Wang, P.-H.; CHIA-LIN YANG ; CHIA-LIN YANG | Proceedings - Design Automation Conference | 0 | 0 | |
| 2018 | Active forwarding: eliminate IOMMU address translation for accelerator-rich architectures. | Fu, Hsueh-Chun; Wang, Po-Han; Yang, Chia-Lin; CHIA-LIN YANG | Proceedings of the 55th Annual Design Automation Conference, DAC 2018, San Francisco, CA, USA, June 24-29, 2018 | 0 | 0 | |
| 2012 | Age-based PCM wear leveling with nearly zero search cost | Chen, C.-H.; Hsiu, P.-C.; Kuo, T.-W.; Yang, C.-L.; Wang, C.-Y.M.; TEI-WEI KUO ; CHIA-LIN YANG | Design Automation Conference | 80 | 0 | |
| 2012 | Age-based PCM wear leveling with nearly zero search cost. | Chen, Chi-Hao; Hsiu, Pi-Cheng; Kuo, Tei-Wei; Yang, Chia-Lin; Wang, Cheng-Yuan Michael; CHIA-LIN YANG | The 49th Annual Design Automation Conference 2012, DAC '12, San Francisco, CA, USA, June 3-7, 2012 | 80 | 0 | |
| 2012 | Age-based PCM wear leveling with nearly zero search cost. | Chen, Chi-Hao; Hsiu, Pi-Cheng; Kuo, Tei-Wei; Yang, Chia-Lin; TEI-WEI KUO ; CHIA-LIN YANG | The 49th Annual Design Automation Conference 2012, DAC '12, San Francisco, CA, USA, June 3-7, 2012 | 80 | 0 | |
| 2010 | An analytical model to exploit memory task scheduling | Cheng, H.-Y.; Li, J.; Yang, C.-L.; CHIA-LIN YANG | Annual Workshop on Interaction between Compilers and Computer Architectures | 2 | 0 | |
| 2007 | An architectural co-synthesis algorithm for energy-aware network-on-chip design | Hung, Wei-Hsuan; Chen, Yi-Jung; Yang, Chia-Lin; Chang, Yen-Sheng; Su, Alan P.; CHIA-LIN YANG | ACM Symposium on Applied Computing | 4 | 0 | |
| 2009 | An Architectural Co-Synthesis Algorithm for Energy-Aware Network-on-Chip Design | Chen, Yi-Jung; Yang, Chia-Lin ; Chang, Yen-Sheng | Journal of Systems Architecture | 12 | 10 | |
| 2017 | Analyzing opencl 2.0 workloads using a heterogeneous CPU-GPU simulator | Wang, L.; Tsai, R.-W.; Wang, S.-C.; Chen, K.-C.; Wang, P.-H.; Cheng, H.-Y.; Lee, Y.-C.; Shu, S.-J.; Yang, C.-C.; Hsu, M.-Y.; Kan, L.-C.; Lee, C.-L.; Yu, T.-C.; Peng, R.-D.; Yang, C.-L.; Hwang, Y.-S.; Lee, J.-K.; Tsao, S.-L.; CHIA-LIN YANG ; MING OUHYOUNG | ISPASS 2017 - IEEE International Symposium on Performance Analysis of Systems and Software | 3 | 0 | |
