公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
2004 | A 10 Gbase-LX4 receiver front end transimpedance amplifier and limiting amplifier | Tsai, Hung-Chieh; Yeh, Jyh-Yih; Tu, Wei-Hsuan; Lee, Tai-Cheng ; Wang, Chorng-Kuang | 2004 International Symposium on Circuits and Systems, 2004. ISCAS '04 | | | |
2004 | A 10 Gbase-LX4 receiver front end transimpedance amplifier and limiting amplifier. | Tsai, Hung-Chieh; Yeh, Jyh-Yih; Tu, Wei-Hsuan; Lee, Tai-Cheng; Wang, Chorng-Kuang; TAI-CHENG LEE | Proceedings of the 2004 International Symposium on Circuits and Systems, ISCAS 2004, Vancouver, BC, Canada, May 23-26, 2004 | | | |
2018 | A 10-bit 2.6-GS/s Time-Interleaved SAR ADC with a Digital-Mixing Timing-Skew Calibration Technique | Lin, C.-Y.; Wei, Y.-H.; Lee, T.-C.; TAI-CHENG LEE | IEEE Journal of Solid-State Circuits | 50 | 48 | |
2011 | A 10-bit 400-MS/s 36-mW interleaved ADC | Huang, Y.-C.; Lin, C.-Y.; Lee, T.-C.; TAI-CHENG LEE | 2011 IEEE International Symposium on Radio-Frequency Integration Technology, RFIT 2011 | 2 | 0 | |
2010 | A 10-bit piplined A/D converter with split calibration and opamp-sharing technique | Hung, L.-H.; Huang, Y.-C.; Lee, T.-C.; TAI-CHENG LEE | Proceedings of 2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010 | 0 | 0 | |
2017 | A 10-Gb/s Equalizer with Digital Adaptation | J-C Hsiao; T-C Lee; TAI-CHENG LEE | International SoC Design Conference | 0 | 0 | |
2010 | A 10b 100MS/s 4.5mW pipelined ADC with a time sharing technique | Huang, Y.-C.; Lee, T.-C.; TAI-CHENG LEE | Digest of Technical Papers - IEEE International Solid-State Circuits Conference | 29 | 0 | |
2018 | A 10b 2.6GS/s Time-Interleaved SAR ADC with Background Timing-Skew Calibration | C-Y Lin; Y-H Wei; T-C Lee; TAI-CHENG LEE | IEEE Journal of Solid-State Circuits | 29 | 0 | |
2008 | 10GBase-T乙太網路系統晶片設計-子計畫三:適用於10GBase-T乙太網路接收機之類比前端電路(1/2) | 李泰成 | | | | |
2008 | 10GBase-T乙太網路系統晶片設計-子計畫三:適用於10GBase-T乙太網路接收機之類比前端電路(2/2) | 李泰成 | | | | |
2016 | A 12-bit 210-MS/s 2-Times Interleaved Pipelined-SAR ADC With a Passive Residue Transfer Technique | C-Y Lin; T-C Lee; TAI-CHENG LEE | IEEE Transactions on Circuits and Systems, Part I | 24 | 22 | |
0 | A 12-bit 600-MS/s time-interleaved SAR ADC with background timing skew calibration | 5. Y-H Wei; C-Y Lin; T-C Lee; TAI-CHENG LEE | IEEE International Symposium on Radio-Frequency Integration Technology (RFIT) | 13 | 0 | |
2001 | A 125-MHz mixed-signal echo canceller for Gigabit Ethernet on copper wire | Lee, T.-C.; Razavi, B.; TAI-CHENG LEE | IEEE Journal of Solid-State Circuits | 26 | 19 | |
2014 | A 2.3GHz fractional-N dividerless phase-locked loop with -112dBc/Hz in-band phase noise | Huang, P.-C.; Chang, W.-S.; Lee, T.-C.; TAI-CHENG LEE | Digest of Technical Papers - IEEE International Solid-State Circuits Conference | 33 | 0 | |
2014 | 2.4-GHz High-Efficiency Adaptive Power Harvester | C-C Lee; T-C Lee; TAI-CHENG LEE | IEEE Transactions on Very Large Scale Integration Systems | 56 | 49 | |
2014 | A 20-MHz BW 75-dB SFDR shifted-averaging VCO-based ΔΣ modulator. | Kang, Yu-Hsuan; Lin, Chin-Yu; Lee, Tai-Cheng; TAI-CHENG LEE | IEEE International Symposium on Circuits and Systemss, ISCAS 2014, Melbourne, Victoria, Australia, June 1-5, 2014 | 0 | 0 | |
2016 | A 200-MS/s Phase-Detector-Based Comparator with 400-uVrms Noise | C-Y Lin; C-H Wong; C-H Hsu; Y-H Wei; T-C Lee; TAI-CHENG LEE | IEEE Transactions on Circuits and Systems, Part II | | | |
2016 | A 200-MS/s phase-detector-based comparator with 400-μVrms noise | Lin, C.-Y.; Wong, C.-H.; Hsu, C.-H.; Wei, Y.-H.; TAI-CHENG LEE | IEEE Transactions on Circuits and Systems II: Express Briefs | 3 | 3 | |
2016 | A 2X25Gb/s 20mW serializing transmitter with 2.5:1 multiplexers in 40nm technology | B-C Lin; W-S Chang; T-C Lee; TAI-CHENG LEE | IEEE VLSI-DAT | 0 | 0 | |
2016 | A 5 GHz Fractional- N ADC-Based Digital Phase-Locked Loops With ?243.8 dB FOM | W-S Chang; T-C Lee; TAI-CHENG LEE | IEEE Transactions on Circuits and Systems, Part I | | | |