公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
2013 | 100Gb/s ethernet chipsets in 65nm CMOS technology | Jiang, J.-Y.; Chiang, P.-C.; Hung, H.-W.; Lin, C.-L.; Yoon, T.; Lee, J.; JRI LEE | Digest of Technical Papers - IEEE International Solid-State Circuits Conference | 63 | 0 | |
2010 | A 2 x 25-Gb/s Receiver With 2:5 DMUX for 100-Gb/s Ethernet | Wu, Ke-Chung; Lee, Jri; JRI LEE | Ieee Journal of Solid-State Circuits | 23 | 17 | |
2006 | A 20-Gb/s Adaptive Equalizer in 0.13 um CMOS Technology | Lee, Jri | IEEE Journal of Solid-State Circuits | | | |
2008 | A 20-Gb/s burst-mode clock and data recovery circuit using injection-locking technique | JRI LEE ; Liu, M. | IEEE Journal of Solid-State Circuits | 56 | 53 | |
2009 | A 20-Gb/s Full-Rate Linear Clock and Data Recovery Circuit With Automatic Frequency Acquisition | Lee, Jri; Wu, Ke-Chung; JRI LEE | Ieee Journal of Solid-State Circuits | 53 | 45 | |
2007 | A 20Gb/s burst-mode CDR circuit using injection-locking technique | Lee, J.; Mingohung, L.; JRI LEE | Digest of Technical Papers - IEEE International Solid-State Circuits Conference | 30 | 0 | |
2008 | A 20Gb/s Duobinary Transceiver in 90nm CMOS. | Lee, Jri; Chen, Ming-Shuan; Wang, Huaide; JRI LEE | 2008 IEEE International Solid-State Circuits Conference, ISSCC 2008, Digest of Technical Papers, San Francisco, CA, USA, February 3-7, 2008 | 13 | 0 | |
2009 | A 20Gb/s full-rate linear CDR circuit with automatic frequency acquisition | Lee, J.; Wu, K.-C.; JRI LEE | Digest of Technical Papers - IEEE International Solid-State Circuits Conference | 16 | 0 | |
2010 | A 21-Gb/s 87-mW transceiver with FFE/DFE/analog equalizer in 65-nm CMOS technology | Wang, H.; Lee, J.; JRI LEE | IEEE Journal of Solid-State Circuits | 94 | 84 | |
2010 | A 2x25Gb/s deserializer with 2:5 DMUX for 100Gb/s ethernet applications | Wu, K.-C.; Lee, J.; JRI LEE | Digest of Technical Papers - IEEE International Solid-State Circuits Conference | 17 | 0 | |
2005 | 40Gb/s CMOS 光纖通訊收發系統 | 李致毅 | | | | |
2011 | A 40Gb/s TX and RX chip set in 65nm CMOS | Chen, M.-S.; Shih, Y.-N.; Lin, C.-L.; Hung, H.-W.; Lee, J.; JRI LEE | Digest of Technical Papers - IEEE International Solid-State Circuits Conference | 20 | 0 | |
2015 | 4?25 Gb/s transceiver with optical front-end for 100 GbE system in 65 nm CMOS technology | Chiang, P.-C.; Jiang, J.-Y.; Hung, H.-W.; Wu, C.-Y.; Chen, G.-S.; Lee, J.; JRI LEE | IEEE Journal of Solid-State Circuits | 42 | 39 | |
2017 | A 56Gb/s PAM-4/NRZ transceiver in 40nm CMOS | Peng, P.-J.; Li, J.-F.; Chen, L.-Y.; Lee, J.; JRI LEE | Digest of Technical Papers - IEEE International Solid-State Circuits Conference | 80 | 0 | |
2015 | 56Gb/s PAM4 and NRZ SerDes transceivers in 40nm CMOS | Lee, J.; Chiang, P.-C.; Weng, C.-C.; JRI LEE | IEEE Symposium on VLSI Circuits, Digest of Technical Papers | 13 | 0 | |
2008 | A 6-b 1-GS/s 30-mW ADC in 90-nm CMOS technology | Lien, Y.-C.; Lee, J.; JRI LEE | Proceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008 | 7 | 0 | |
2010 | A 60-GHz FSK transceiver with automatically-calibrated demodulator in 90-nm CMOS | Wang, H.; Hung, M.-H.; Yeh, Y.-C.; Lee, J.; JRI LEE | IEEE Symposium on VLSI Circuits, Digest of Technical Papers | 23 | 0 | |
2014 | 60Gb/s NRZ and PAM4 transmitters for 400GbE in 65nm CMOS | Chiang, P.-C.; Hung, H.-W.; Chu, H.-Y.; Chen, G.-S.; Lee, J.; JRI LEE | Digest of Technical Papers - IEEE International Solid-State Circuits Conference | 46 | 0 | |
2008 | A 75-GHz phase-locked loop in 90-nm CMOS technology | Lee, J.; Liu, M.; Wang, H.; JRI LEE | IEEE Journal of Solid-State Circuits | 94 | 70 | |
2007 | A 75-GHz PLL in 90-nm CMOS technology | Lee, J.; JRI LEE | Digest of Technical Papers - IEEE International Solid-State Circuits Conference | 34 | 0 | |