公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
2022 | 2D Materials-Based Static Random-Access Memory | Liu C.-J; Wan Y; Li L.-J; Lin C.-P; Hou T.-H; Huang Z.-Y; VITA PI-HO HU | Advanced Materials | 10 | 14 | |
2020 | 3D integration of vertical-stacking of MoS2and Si CMOS featuring embedded 2T1R configuration demonstrated on full wafers | Su, Chunjung; Huang, Minkun; Lee, K. S.; VITA PI-HO HU ; Huang, Y. F.; Zheng, B. C.; Yao, C. H.; Lin, Neichih; Kao, Kuo-Hsing Hsing; Hong, Tzu Chieh; Sung, Pojung; Wu, Chienting; Yu, Tungyuan; Lin, Kun–Lin; Tseng, Y. C.; Lin, C. L.; Lee, Yaojen; Chao, Tiensheng; JIUN-YUN LI ; Wu, Wenfa; Shieh, Jiaming; Wang, Yeong-Her; Yeh, Wenkuan | Technical Digest - International Electron Devices Meeting, IEDM | 5 | 0 | |
2015 | Analysis of GeOI FinFET 6T SRAM Cells With Variation-Tolerant WLUD Read-Assist and TVC Write-Assist | M.-L. Fan; P. Su; C.-T. Chuang; VITA PI-HO HU | IEEE Transactions on Electron Devices | 13 | 9 | |
2018 | Analysis of heterojunction GaAs1-xSbx/In1-yGayAs tunnel FETs considering line tunneling | Wang C.-T; Hu V.P.-H.; VITA PI-HO HU | Proceedings - 2018 7th International Symposium on Next-Generation Electronics, ISNE 2018 | 0 | 0 | |
2023 | Analysis of Monolithic 3D SRAM with Back-End-of-Line-compatible Transistors | Lu, Yu Cheng; Lee, Ming; Huang, Zi Yuan; VITA PI-HO HU | 2023 International VLSI Symposium on Technology, Systems and Applications, VLSI-TSA/VLSI-DAT 2023 - Proceedings | 0 | 0 | |
2018 | Analysis of Negative Capacitance UTB SOI MOSFETs considering Line-Edge Roughness and Work Function Variation | Chiu P.-C; Hu V.P.-H.; VITA PI-HO HU | 2018 IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2018 - Proceedings | 4 | 0 | |
2013 | Analysis of Single-Trap-Induced Random Telegraph Noise and its Interaction With Work Function Variation for Tunnel FET | M.-L. Fan; V. P.-H. Hu; Y.-N. Chen; P. Su; C.-T. Chuang; VITA PI-HO HU ; M.-L. Fan; V. P.-H. Hu; Y.-N. Chen; P. Su; C.-T. Chuang; 胡璧合 | IEEE Transactions on Electron Devices | 55 | 48 | |
2012 | Analysis of Single-Trap-Induced Random Telegraph Noise on FinFET Devices, 6T SRAM Cell, and Logic Circuits | M.-L. Fan; Y.-N. Chen; P. Su; C.-T. Chuang; VITA PI-HO HU | IEEE Transactions on Electron Devices | 39 | 34 | |
2017 | Analysis of subthreshold swing and internal voltage amplification for hysteresis-free negative capacitance FinFETs | Chiu P.-C; Hu V.P.-H.; VITA PI-HO HU | 2017 IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2017 - Proceedings | 5 | 0 | |
2018 | Analysis of switching characteristics for negative capacitance ultra-thin-body germanium-on-insulator MOSFETs | P.-C. Chiu; VITA PI-HO HU | Japanese Journal of Applied Physics | 1 | 2 | |
2011 | Analysis of Ultra-Thin-Body SOI Subthreshold SRAM Considering Line-Edge Roughness, Work Function Variation, and Temperature Sensitivity | M.-L. Fan; P. Su; C.-T. Chuang; VITA PI-HO HU | IEEE Journal on Emerging and Selected Topics in Circuits and Systems | 4 | 4 | |
2012 | Band-to-Band-Tunneling Leakage Suppression for Ultra-Thin-Body GeOI MOSFETs Using Transistor Stacking | M.-L. Fan; P. Su; C.-T. Chuang; VITA PI-HO HU | IEEE Electron Device Letters | 14 | 10 | |
2019 | Comparative Analysis of Negative Capacitance Junctionless and Inversion Mode Transistors for Low Power Applications | Gupta M; Hu V.P.-H.; VITA PI-HO HU | 2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2019 | 0 | 0 | |
2013 | Comparative Leakage Analysis of GeOI FinFET and Ge Bulk FinFET | V. P.-H. Hu; M.-L. Fan; P. Su; C.-T. Chuang; VITA PI-HO HU ; V. P.-H. Hu; M.-L. Fan; P. Su; C.-T. Chuang; 胡璧合 | IEEE Transactions on Electron Devices | 22 | 20 | |
2011 | Comparison of 4T and 6T FinFET SRAM cells for subthreshold operation considering variability-A model-based approach | Fan M.-L; Wu Y.-S; VITA PI-HO HU ; Hsieh C.-Y; Su P; Chuang C.-T. | IEEE Transactions on Electron Devices | 34 | 22 | |
2021 | Critical Role of GIDL Current for Erase Operation in 3D Vertical FeFET and Compact Long-term FeFET Retention Model | Mo F; Xiang J; Mei X; Sawabe Y; Saraya T; Hiramoto T; Su C.-J; VITA PI-HO HU ; Kobayashi M. | Digest of Technical Papers - Symposium on VLSI Technology | 4 | | |
2013 | Design and Analysis of Robust Tunneling FET SRAM | Y.-N. Chen; M.-L. Fan; V. P.-H. Hu; P. Su; C.-T. Chuang; VITA PI-HO HU ; Y.-N. Chen; M.-L. Fan; V. P.-H. Hu; P. Su; C.-T. Chuang; 胡璧合 | IEEE Transactions on Electron Devices | 36 | 30 | |
2019 | Device Designs and Analog Performance Analysis for Negative-Capacitance Vertical-Tunnel FET | Lin H.-H; Hu V.P.-H.; VITA PI-HO HU | Proceedings - International Symposium on Quality Electronic Design, ISQED | 4 | 0 | |
2018 | Device Designs of III-V Tunnel FETs for Performance Enhancements through Line Tunneling | Wang C.-T; Hu V.P.-H.; VITA PI-HO HU | 2018 IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2018 - Proceedings | 4 | 0 | |
2022 | Efficient Erase Operation by GIDL Current for 3D Structure FeFETs with Gate Stack Engineering and Compact Long-Term Retention Model | Mo F; Xiang J; Mei X; Sawabe Y; Saraya T; Hiramoto T; Su C.-J; VITA PI-HO HU ; Kobayashi M. | IEEE Journal of the Electron Devices Society | 3 | 3 | |