| Issue Date | Title | Author(s) | Source | scopus | WOS | Fulltext/Archive link |
| 2022 | 2D Materials-Based Static Random-Access Memory | Liu C.-J; Wan Y; Li L.-J; Lin C.-P; Hou T.-H; Huang Z.-Y; VITA PI-HO HU | Advanced Materials | 5 | 9 | |
| 2020 | 3D integration of vertical-stacking of MoS2and Si CMOS featuring embedded 2T1R configuration demonstrated on full wafers | JIUN-YUN LI et al. ; VITA PI-HO HU et al. | Technical Digest - International Electron Devices Meeting, IEDM | 4 | 0 | |
| 2015 | Analysis of GeOI FinFET 6T SRAM Cells With Variation-Tolerant WLUD Read-Assist and TVC Write-Assist | M.-L. Fan; P. Su; C.-T. Chuang; VITA PI-HO HU | IEEE Transactions on Electron Devices | 14 | 8 | |
| 2018 | Analysis of heterojunction GaAs1-xSbx/In1-yGayAs tunnel FETs considering line tunneling | Wang C.-T; Hu V.P.-H.; VITA PI-HO HU | Proceedings - 2018 7th International Symposium on Next-Generation Electronics, ISNE 2018 | 0 | 0 | |
| 2018 | Analysis of Negative Capacitance UTB SOI MOSFETs considering Line-Edge Roughness and Work Function Variation | Chiu P.-C; Hu V.P.-H.; VITA PI-HO HU | 2018 IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2018 - Proceedings | 4 | 0 | |
| 2013 | Analysis of Single-Trap-Induced Random Telegraph Noise and its Interaction With Work Function Variation for Tunnel FET | M.-L. Fan; V. P.-H. Hu; Y.-N. Chen; P. Su; C.-T. Chuang; VITA PI-HO HU ; M.-L. Fan; V. P.-H. Hu; Y.-N. Chen; P. Su; C.-T. Chuang; 胡璧合 ; VITA PI-HO HU | IEEE Transactions on Electron Devices | 53 | 47 | |
| 2012 | Analysis of Single-Trap-Induced Random Telegraph Noise on FinFET Devices, 6T SRAM Cell, and Logic Circuits | M.-L. Fan; Y.-N. Chen; P. Su; C.-T. Chuang; VITA PI-HO HU | IEEE Transactions on Electron Devices | 38 | 34 | |
| 2017 | Analysis of subthreshold swing and internal voltage amplification for hysteresis-free negative capacitance FinFETs | Chiu P.-C; Hu V.P.-H.; VITA PI-HO HU | 2017 IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2017 - Proceedings | 5 | 0 | |
| 2018 | Analysis of switching characteristics for negative capacitance ultra-thin-body germanium-on-insulator MOSFETs | P.-C. Chiu; VITA PI-HO HU | Japanese Journal of Applied Physics | 1 | 2 | |
| 2011 | Analysis of Ultra-Thin-Body SOI Subthreshold SRAM Considering Line-Edge Roughness, Work Function Variation, and Temperature Sensitivity | M.-L. Fan; P. Su; C.-T. Chuang; VITA PI-HO HU | IEEE Journal on Emerging and Selected Topics in Circuits and Systems | 4 | 4 | |
| 2012 | Band-to-Band-Tunneling Leakage Suppression for Ultra-Thin-Body GeOI MOSFETs Using Transistor Stacking | M.-L. Fan; P. Su; C.-T. Chuang; VITA PI-HO HU | IEEE Electron Device Letters | 13 | 10 | |
| 2019 | Comparative Analysis of Negative Capacitance Junctionless and Inversion Mode Transistors for Low Power Applications | Gupta M; Hu V.P.-H.; VITA PI-HO HU | 2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2019 | 0 | 0 | |
| 2013 | Comparative Leakage Analysis of GeOI FinFET and Ge Bulk FinFET | V. P.-H. Hu; M.-L. Fan; P. Su; C.-T. Chuang; VITA PI-HO HU ; V. P.-H. Hu; M.-L. Fan; P. Su; C.-T. Chuang; 胡璧合 ; VITA PI-HO HU | IEEE Transactions on Electron Devices | 20 | 18 | |
| 2013 | Design and Analysis of Robust Tunneling FET SRAM | Y.-N. Chen; M.-L. Fan; V. P.-H. Hu; P. Su; C.-T. Chuang; VITA PI-HO HU ; Y.-N. Chen; M.-L. Fan; V. P.-H. Hu; P. Su; C.-T. Chuang; 胡璧合 ; VITA PI-HO HU | IEEE Transactions on Electron Devices | 35 | 29 | |
| 2019 | Device Designs and Analog Performance Analysis for Negative-Capacitance Vertical-Tunnel FET | Lin H.-H; Hu V.P.-H.; VITA PI-HO HU | Proceedings - International Symposium on Quality Electronic Design, ISQED | 3 | 0 | |
| 2018 | Device Designs of III-V Tunnel FETs for Performance Enhancements through Line Tunneling | Wang C.-T; Hu V.P.-H.; VITA PI-HO HU | 2018 IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2018 - Proceedings | 4 | 0 | |
| 2020 | Energy-Efficient Monolithic 3-D SRAM Cell with BEOL MoS<inf>2</inf>FETs for SoC Scaling | Su, C.-W.; Lee, Y.-W.; Ho, T.-Y.; Cheng, C.-C.; Chen, T.-C.; Hung, T.Y.-T.; Li, J.-F.; Chen, Y.-G.; Li, L.-J.; VITA PI-HO HU | IEEE Transactions on Electron Devices | 7 | 7 | |
| 2019 | Evaluation of analog circuit performance for ferroelectric SOI MOSFETs considering interface trap charges and gate length variations | Lu Y.-C; Hu V.P.-H.; VITA PI-HO HU | 2019 Silicon Nanoelectronics Workshop, SNW 2019 | 7 | 0 | |
| 2016 | Evaluation of Monolayer and Bilayer 2-D Transition Metal Dichalcogenide Devices for SRAM Applications | C.-H. Yu; M.-L. Fan; K.-C. Yu; Pin Su; C.-T. Chuang; VITA PI-HO HU | IEEE Transactions on Electron Devices | 16 | 17 | |
| 2014 | Evaluation of Stabilit, Performance of Ultra-Low Voltage MOSFET, TFET, and Mixed TFET-MOSFET SRAM Cell With Write-Assist Circuits | Y.-N. Chen; M.-L. Fan; V. P.-H. Hu; Pin Su; C.-T. Chuang; VITA PI-HO HU ; Y.-N. Chen; M.-L. Fan; V. P.-H. Hu; Pin Su; C.-T. Chuang; 胡璧合 ; VITA PI-HO HU | IEEE Journal on Emerging and Selected Topics in Circuits and Systems | 41 | 35 | |
