公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
2004 | Fast Postplacement Optimization Using Functional Symmetries | Chang, C.-W.; Hsiao, M.-F.; Hu, B.; Wang, K.; Marek-Sadowska, M.; Cheng, C.-K.; SAO-JIE CHEN | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 13 | 2 | |
2008 | Flow maximization for NoC routing algorithms | Lan, Y.-C.; Chen, M.C.; Su, A.P.; Hu, Y.-H.; Chen, S.-J.; SAO-JIE CHEN | IEEE Computer Society Annual Symposium on VLSI: Trends in VLSI Technology and Design, ISVLSI 2008 | 3 | 0 | |
2008 | Fluidity concept for NoC: A congestion avoidance and relief routing scheme | Lan, Y.-C.; Chen, M.C.; Su, A.P.; Hu, Y.-H.; Chen, S.-J.; SAO-JIE CHEN | 2008 IEEE International SOC Conference, SOCC | 9 | 0 | |
2010 | Formal modeling and verification for Network-on-chip | Chen, Y.-R.; Su, W.-T.; Hsiung, P.-A.; Lan, Y.-C.; Hu, Y.-H.; Chen, S.-J.; SAO-JIE CHEN | 1st International Conference on Green Circuits and Systems, ICGCS 2010 | 18 | 0 | |
2001 | Formal verification of embedded real-time software in component-based application frameworks | Hsiung, P.-A.; See, W.-B.; Lee, T.-Y.; Fu, J.-M.; Chen, S.-J.; SAO-JIE CHEN | Asia-Pacific Software Engineering Conference and International Computer Science Conference, APSEC and ICSC | | | |
1996 | FPGA技術映射和繞線方法之研究 | 陳少傑 | | | | |
2003 | Framework approach for system on chip software development | See, W.-B.; Hsiung, P.-A.; Chen, S.-J.; SAO-JIE CHEN | International Symposium on VLSI Technology, Systems, and Applications | 2 | 0 | |
1991 | GEAR: a general area router using planning approach | Chen, Yuh-Lin; SAO-JIE CHEN ; Tsai, Chia-Chun; Hu, Yu-Hen | International Symposium on VLSI Technology, Systems, and Applications, Proceedings | 0 | 0 | |
1994 | General area router based on planning techniques | SAO-JIE CHEN ; Tsai, C.-C.; Chen, Y.-L.; Hu, Y.-H. | IEE Proceedings: Computers and Digital Techniques | 0 | 0 | |
1989 | Generalized Terminal Connectivity Problem for Multi-Layer Layout Scheme | Tsai, C. C.; 馮武雄; 陳少傑 ; Hsiao, P, Y.; Chen, H. F.; Feng, Wu-Shiung; Chen, Sao-Jie | 1989 Joint Technical Conference on Circuits/Systems, Computers and Communications | | | |
1990 | Generalized terminal connectivity problem for multilayer layout scheme | Tsai, C.-C.; SAO-JIE CHEN ; Feng, W.-S. | Computer-Aided Design | 1 | 0 | |
1989 | GM Plan: A gate matrix layout algorithm based on artificial intelligence planning techniques | SAO-JIE CHEN | IEEE International Symposium on Circuits and Systems | | | |
1990 | GM-Learn: an iterative learning algorithm for CMOS gate matrix layout | Chen, Sao-Jie ; Hu, Yu Hen | IEE Proceedings E: Computers and Digital Techniques | | | |
1989 | GM-Learn:an Iterative Learning Algorithm for CMOS Gate Matrix Layout | 陳少傑 ; Hu, Y. H.; Chen, Sao-Jie | 1989 International Symposium on Circuits and Systems | | | |
1989 | GM_Learn: an iterative learning algorithm for CMOS gate matrix layout | Chen, Sao-Jie ; Hu, Yu Hen | IEEE International Symposium on Circuits and Systems | 0 | 0 | |
1990 | GM_Plan: A Gate Matrix Layout Algorithm Based on Artificial Intelligence Planning Techniques | Hu, Y.H.; Chen, S.-J.; SAO-JIE CHEN | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 17 | 15 | |
1989 | An H-V Tile-Expansion Router | Tsai, C. C.; 陳少傑 ; 馮武雄; Chen, Sao-Jie ; Feng, Wu-Shiung | National Computer Symposium | | | |
2000 | Hard ware-software timing co-verification of distributed embedded systems | Jih-Ming, F.U.; Lee Trong-Yen; Hsiung, P.-A.; SAO-JIE CHEN | IEICE Transactions on Information and Systems | 10 | | |
2015 | Hardware implementation of a real-time distributed video decoder | Yang, H.-P.; Ho, M.-H.; Hsieh, H.-C.; Cheng, P.-H.; Chen, S.-J.; SAO-JIE CHEN | International Conference on Digital Signal Processing, DSP | 1 | 0 | |
2009 | Hardware software co-design of a multimedia SOC platform | Hu, Yu-Hen; Hsiung, Pao-Ann; Lin, Guang-Huei; Chen, Sao-Jie | | 0 | 0 | |