公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
---|---|---|---|---|---|---|
2013 | An ultrasynchronization checking method with trace-driven simulation for fast and accurate MPSoC virtual platform simulation | Yeh, Y.-F.; Lin, H.-C.; Huang, C.-Y.; CHUNG-YANG HUANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 1 | 1 | |
2011 | Using SAT-based Craig interpolation to enlarge clock gating functions. | Lin, Ting-Hao; Huang, Chung-Yang (Ric); CHUNG-YANG HUANG | Proceedings of the 48th Design Automation Conference, DAC 2011, San Diego, California, USA, June 5-10, 2011 | 7 | 0 | |
2001 | Using Word-Level ATPG and Modular Arithmetic Constraint-Solving Techniques for Assertion Property Checking | R.C.-Y. Huang; K.-T. Cheng; CHUNG-YANG HUANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 38 | 31 | |
2007 | 兆級晶片系統前瞻技術研究-子計畫七:兆級晶片系統模擬與正規驗證之整合技術(2/3) | 黃鐘揚 | ||||
2007 | 兆級晶片系統前瞻技術研究-子計畫七:兆級晶片系統模擬與正規驗證之整合技術(3/3) | 黃鐘揚 |