公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
2017 | On static binary translation of ARM/Thumb Mixed ISA binaries | Chen, J.-Y.; Yang, W.; Hsu, W.-C.; Shen, B.-Y.; WEI-CHUNG HSU | ACM Transactions on Embedded Computing Systems | 4 | 4 | |
2002 | On the impact of naming methods for heap-oriented pointers in C programs | Chen, T.; Lin, J.; Hsu, W.-C.; WEI-CHUNG HSU | International Symposium on Parallel Architectures, Algorithms and Networks | 2 | 0 | |
1992 | On the instruction-level characteristics of scalar code in highly-vectorized scientific applications | Vajapeyam, Sriram; WEI-CHUNG HSU | 25th Annual International Symposium on Microarchitecture | 1 | 0 | |
1989 | On the Minimization of Loads/Stores in Local Register Allocation | Hsu, W.-C.; Fischer, C.N.; Goodman, J.R.; WEI-CHUNG HSU | IEEE Transactions on Software Engineering | 34 | 0 | |
2002 | On the Predictability of Program Behavior Using Different Input Data Sets. | Hsu, Wei-Chung; Chen, Howard; Yew, Pen-Chung; Chen, Dong-yuan; WEI-CHUNG HSU | 6th Annual Workshop on Interaction between Compilers and Computer Architecture (INTERACT-6 2002), 3 February 2002, Boston, MA, USA | 26 | 0 | |
1986 | ON THE USE OF REGISTERS VS. CACHE TO MINIMIZE MEMORY TRAFFIC. | Goodman, James R.; Hsu, Wei-Chung; WEI-CHUNG HSU | Annual Symposium on Computer Architecture | | | |
2015 | Optimizing control transfer and memory virtualization in full system emulators | Hong, D.-Y.; Hsu, C.-C.; Chou, C.-Y.; Hsu, W.-C.; Liu, P.; WEI-CHUNG HSU ; PANGFENG LIU | ACM Transactions on Architecture and Code Optimization | 5 | 2 | |
2019 | Optimizing data permutations in structured loads/stores translation and SIMD register mapping for a cross-ISA dynamic binary translator | Fu, S.-Y.; Hong, D.-Y.; Liu, Y.-P.; Wu, J.-J.; Hsu, W.-C.; WEI-CHUNG HSU | Journal of Systems Architecture | 0 | 0 | |
2010 | Performance characterization of data mining benchmarks | Mekkat, V.; Natarajan, R.; Zhai, A.; WEI-CHUNG HSU | Proceedings - Annual Workshop on Interaction between Compilers and Computer Architectures, INTERACT | 4 | 0 | |
1993 | Performance of cached DRAM organizations in vector supercomputers | Hsu, W.-C.; Smith, J.E.; WEI-CHUNG HSU | Annual Symposium on Computer Architecture | | | |
1993 | Performance of Cached DRAM Organizations in Vector Supercomputers. | Hsu, Wei-Chung; Smith, James E.; WEI-CHUNG HSU | Proceedings of the 20th Annual International Symposium on Computer Architecture, San Diego, CA, USA, May 1993 | 26 | 0 | |
2005 | Performance of runtime optimization on BLAST | Das, A.; Lu, J.; Chen, H.; Kim, J.; Yew, P.-C.; Hsu, W.-C.; WEI-CHUNG HSU | 2005 International Symposium on Code Generation and Optimization | 6 | 0 | |
2018 | A Pipeline-Based Heterogeneous Framework for Efficient Synthetic Light Field Rendering | Kao, Chih-Chen; Tseng, Liang-Chi; Hsu, Wei-Chung; WEI-CHUNG HSU | Applied Computing Review | 1 | 0 | |
2017 | A Pipeline-Based Ray-Tracing Runtime System for HSA-Compliant Frameworks | Kao, Chih-Chen; Miao, Yu-Tsung; Hsu, Wei-Chung; WEI-CHUNG HSU | Ieee Transactions on Multimedia | 1 | 1 | |
2016 | A pipeline-based runtime technique for improving Ray-Tracing on HSA-compliant systems | Kao, C.-C.; Miao, Y.-T.; WEI-CHUNG HSU | Proceedings - IEEE International Conference on Multimedia and Expo | 3 | 0 | |
2011 | PQEMU: A parallel system emulator based on QEMU | Ding, J.-H.; Chang, P.-C.; Hsu, W.-C.; WEI-CHUNG HSU | International Conference on Parallel and Distributed Systems | 38 | 0 | |
1992 | Prefetching in Supercomputer Instruction Caches. | Smith, James E.; Hsu, Wei-Chung; WEI-CHUNG HSU | Proceedings Supercomputing '92, Minneapolis, MN, USA, November 16-20, 1992 | 25 | 0 | |
2019 | Processor-tracing guided region formation in dynamic binary translation | Hong, D.-Y.; Wu, J.-J.; Liu, Y.-P.; Fu, S.-Y.; Hsu, W.-C.; WEI-CHUNG HSU | ACM Transactions on Architecture and Code Optimization | 1 | 0 | |
2006 | Recovery code generation for general speculative optimizations. | Lin, Jin; Hsu, Wei-Chung; Yew, Pen-Chung; Ju, Roy Dz-Ching; Ngai, Tin-Fook; WEI-CHUNG HSU | TACO | 2 | 0 | |
2009 | Reducing code size by graph coloring register allocation and assignment algorithm for mixed-width ISA processor | Wang, J.-S.; Wu, I-W.; Chen, Y.-S.; Shann, J.J.-J.; WEI-CHUNG HSU | 12th IEEE International Conference on Computational Science and Engineering | 0 | 0 | |