公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
2005 | A 10-Gb/s CMOS Adaptive Equalizer for Backplane Applications | SriKanth Gondi; Jri Lee; Behzad Razavi; JRI LEE | International Solid-State Circuits Conference | 63 | 0 | |
2005 | A 20-Gb/s 2-to-1 MUX and a 40-GHz VCO in 0.18-μm CMOS technology | JRI LEE ; Jian-yu Ding; Tuan-yi Cheng | IEEE Symposium on VLSI Circuits, Digest of Technical Papers | 13 | 0 | |
2006 | A 20-Gb/s Adaptive Equalizer in 0.13 μm CMOS Technology | JRI LEE | IEEE Journal of Solid-State Circuits | | | |
2006 | A 20-Gb/s Adaptive Equalizer in 0.13-μm CMOS Technology | JRI LEE | International Solid-State Circuits Conference | | | |
2007 | A 20-Gb/s Burst-Mode CDR in 90-nm CMOS | Jri Lee; M. Liu; JRI LEE | International Solid-State Circuits Conference | | | |
2007 | A 20Gb/s broadband transmitter with auto-configuration technique | Jri Lee; Huaide Wang; JRI LEE | International Solid-State Circuits Conference | 10 | 0 | |
2008 | A 20Gb/s duobinary transceiver in 90nm CMOS | Jri Lee; M. Chen; H. Wang; JRI LEE | International Solid-State Circuits Conference | 13 | 0 | |
2006 | A 3-to-8-GHz Fast Hopping Frequency Synthesizer in 0.18-μm CMOS Technology | JRI LEE | IEEE Journal of Solid-State Circuits | | | |
2003 | A 40-Gb/s clock and data recovery circuit in 0.18-μm CMOS technology | Lee, J.; Razavi, B.; JRI LEE | IEEE Journal of Solid-State Circuits | 117 | 95 | |
2004 | A 40-GHz Frequency Divider in 0.18-μm CMOS Technology | Lee, J.; Razavi, B.; JRI LEE | IEEE Journal of Solid-State Circuits | 180 | 153 | |
2005 | A 7-band 3-8GHz frequency synthesizer with 1ns band-switching time in 0.18μm CMOS technology | Jri Lee; Da-wei Chiu; JRI LEE | International Solid-State Circuits Conference | 43 | 0 | |
2007 | A 75GHz PLL in 90nmCMOS | JRI LEE | International Solid-State Circuits Conference | | | |
2004 | Analysis and modeling of bang-bang clock and data recovery circuits | Lee, J.; Kundert, K.S.; Razavi, B.; JRI LEE | IEEE Journal of Solid-State Circuits | 199 | 166 | |
2005 | Correction to ?雓?0-Gb/s Clock and Data Recovery Circuit in 0.18-?m CMOS Technology??"Lee | J.; Razavi; JRI LEE | IEEE Journal of Solid-State Circuits | 0 | 0 | |
2016 | CW/FMCW/pulse radar engines for 24/26GHz multi-standard applications in 65nm CMOS | Chen, L.-Y.; Peng, P.-J.; Kao, C.; Chen, Y.-L.; Lee, J.; JRI LEE | 2015 IEEE Asian Solid-State Circuits Conference, A-SSCC 2015 - Proceedings | 2 | 0 | |
2005 | Design and Analysis of a 20-GHz Clock Multiplication Unit in 0.18-μm CMOS Technology | Jri Lee; Shanghann Wu; JRI LEE | Symposium on VLSI Circuits | 4 | 0 | |
2008 | Design and comparison of three 20-Gb/s backplane transceivers for duobinary, PAM4, and NRZ data | JRI LEE ; Chen, M.-S.; Wang, H.-D. | IEEE Journal of Solid-State Circuits | 122 | 105 | |
2015 | Design of 56 Gb/s NRZ and PAM4 SerDes transceivers in CMOS technologies | Lee, J.; Chiang, P.-C.; Peng, P.-J.; Chen, L.-Y.; Weng, C.-C.; JRI LEE | IEEE Journal of Solid-State Circuits | 107 | 95 | |
1998 | Design of spiral inductors on silicon substrates with a fast simulator | Lee, J.; Kral, A.; Abidi, A.A.; Alexopoulos, N.G.; JRI LEE | European Solid-State Circuits Conference | 30 | 0 | |
1998 | Efficient frequency conversion apparatus for use with nultimode solid-state lasers | rew Kung; Jri Lee; JRI LEE | | | | |