公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
2013 | Test generation of path delay faults induced by defects in power TSV | Shih, C.-J.; Hsieh, S.-A.; Lu, Y.-C.; Li, J.C.-M.; Wu, T.-L.; TZONG-LIN WU ; YI-CHANG LU ; CHIEN-MO LI | Proceedings of the Asian Test Symposium | 2 | 0 | |
2014 | Testing of TSV-induced small delay faults for 3-D integrated circuits | Chun-Yi Kuo; Chi-Jih Shih; Yi-Chang Lu; James C.-M. Li; Krishnendu Chakrabarty; YI-CHANG LU ; CHIEN-MO LI | IEEE Trans. Very Large Scale Integration (VLSI) Systems | 17 | 13 | |
2012 | The effect of NBTI on 3D integrated circuits | Cheng-Hong Lin; Yi-Chang Lu; Chin-Khai Tang; Kuen-Yu Tsai; YI-CHANG LU ; KUEN-YU TSAI | Electrical Design of Advanced Packaging and Systems Symposium (EDAPS), 2012 IEEE | 2 | 0 | |
2013 | Thermal coupling aware task migration using neighboring core search for many-core systems. | Mizunuma, Hitoshi; Lu, Yi-Chang; YI-CHANG LU ; CHIA-LIN YANG | 2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013, Hsinchu, Taiwan, April 22-24, 2013 | 8 | 0 | |
2011 | Thermal modeling and analysis for 3-D ICs with integrated microchannel cooling | Mizunuma, H.; Lu, Y.-C.; Yang, C.-L.; YI-CHANG LU ; CHIA-LIN YANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 46 | 46 | |
2011 | Thermal modeling and analysis for 3D-ICs with integrated microchannel cooling | Hitoshi Mizunuma; Yi-Chang Lu; Chia-Lin Yang; YI-CHANG LU | IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems | | | |
2009 | Thermal modeling and device noise properties of 3D-SOI technology | Tze Wee Chen; Jung Hoon Chun; Yi-Chang Lu; Reza Navid; Wei Wang; Chang-Lee Chen; Robert W. Dutton; YI-CHANG LU | IEEE Trans. Electron Devices | 1 | 0 | |
2009 | Thermal Modeling and Device Noise Properties of Three-Dimensional–SOI Technology | Chen, Tze Wee; Chun, Jung Hoon; Lu, Yi-chang ; Navid, R.; Wang, Wei; Chen, Chang-Lee; Dutton, R.W. | IEEE Transactions on Electron Devices | | | |
2009 | Thermal modeling and device oise properties of three-dimensional-SOI technology | Chen, T.W.; Chun, J.-H.; Lu, Y.-C.; Navid, R.; Wang, W.; Chen, C.-L.; Dutton, R.W.; YI-CHANG LU | IEEE Transactions on Electron Devices | 3 | 1 | |
2009 | Thermal modeling for 3D-ICs with integrated microchannel cooling. | Mizunuma, Hitoshi; Yang, Chia-Lin; YI-CHANG LU ; CHIA-LIN YANG | 2009 International Conference on Computer-Aided Design, ICCAD 2009, San Jose, CA, USA, November 2-5, 2009 | 45 | 0 | |
2010 | Thermal-aware router-sharing architecture for 3D network-on-chip designs | Huang, Y.-R.; Pan, J.-H.; Lu, Y.-C.; YI-CHANG LU | IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS | 6 | 0 | |
2018 | Three-dimensional dynamic programming accelerator for multiple sequence alignment | Ruei-Ting Chien; Yi-Lun Liao; Chien-An Wang; Yu-Cheng Li; Yi-Chang Lu; YI-CHANG LU | IEEE Nordic Circuits and Systems Conference | 2 | 0 | |
2022 | Traceback Memory Reduction for Three-Sequence Alignment Algorithm with Affine Gap Models | Chien, Ruei Ting; Lin, Mao Jan; Yeh, Yang Ming; YI-CHANG LU | Proceedings of 2022 Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, APSIPA ASC 2022 | 0 | 0 | |
2021 | Using Regularity Unit As Guidance for Summarization-Based Image Resizing | Hsiao F.-T; Lin Y.-H; YI-CHANG LU | 2021 International Conference on Visual Communications and Image Processing, VCIP 2021 - Proceedings | 0 | 0 | |
2022 | A Variation-Based Nighttime Image Dehazing Flow With a Physically Valid Illumination Estimator and a Luminance-Guided Coloring Model | Yang C.-H; Lin Y.-H; YI-CHANG LU | IEEE Access | 2 | 2 | |
2008 | 多媒體系統無線傳輸介面之研發-子計畫一:用於高速信號辨識與分類之系統晶片(1/3) | 盧奕璋 | | | | |
2008 | 晶片系統之信號與電源完整性問題 | 盧奕璋 | | | | |