公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
2020 | Improved design and in vivo animal tests of bone-guided cochlear implant microsystem with monopolar biphasic multiple stimulation and neural action potential acquisition | Wang S.-H; Huang Y.-K; Chen C.-Y; Lee C.-F; Yang C.-H; Hung C.-C; Liu C.-H; Ker M.-D; CHIEN-HAO LIU ; CHIA-HSIANG YANG | 2020 IEEE Asian Solid-State Circuits Conference, A-SSCC 2020 | 3 | 0 | |
2019 | An integrated message-passing detector and decoder for polar-coded massive MU-MIMO systems | CHIA-HSIANG YANG ; Chen, Y.-T.; Sun, W.-C.; Cheng, C.-C.; Tsai, T.-L.; Ueng, Y.-L.; CHIA-HSIANG YANG | IEEE Transactions on Circuits and Systems I: Regular Papers | | | |
2017 | Integration of Energy-Recycling Logic and Wireless Power Transfer for Ultra-Low-Power Implantables | H.-T. Lin; Y.-C. Wu; P.-H. Hsieh; C.-H. Yang; CHIA-HSIANG YANG | Int. Symposium Circuits and Systems (ISCAS) | 1 | 0 | |
2018 | Introduction to the Special Section on the 2017 Asian Solid-State Circuits Conference (A-SSCC) | Lin, T.-H.; Yang, C.-H.; TSUNG-HSIEN LIN ; CHIA-HSIANG YANG | IEEE Journal of Solid-State Circuits | 0 | 0 | |
2019 | Iterative Inter-Cell Interference Cancellation Receiver for LDPC-Coded MIMO Systems | CHIA-HSIANG YANG ; Sun, W.-C.; Chen, Y.-T.; Yang, C.-H.; Ueng, Y.-L.; CHIA-HSIANG YANG | IEEE Transactions on Signal Processing | | | |
2020 | Iterative Receiver with a Lattice-Reduction-Aided MIMO Detector for IEEE 802.11ax | CHIA-HSIANG YANG ; Wang Y.-P; Wen C.-C; Kao C.-C; Huang C.-J; Liu D.-Z; CHIA-HSIANG YANG | 2020 IEEE Global Communications Conference, GLOBECOM 2020 - Proceedings | | | |
2019 | An LDPC-Coded SCMA receiver with multi-user iterative detection and decoding | CHIA-HSIANG YANG ; Sun, W.-C.; Su, Y.-C.; Ueng, Y.-L.; CHIA-HSIANG YANG | IEEE Transactions on Circuits and Systems I: Regular Papers | | | |
2018 | Massive MIMO detection VLSI design. | CHIA-HSIANG YANG | 2018 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), Hsinchu, Taiwan, April 16-19, 2018 | | | |
2016 | Method and system for constrained power allocation in the multi-input multi-output systems | C.-H. Yang; C.-E. Chen; C.-W. Jou; CHIA-HSIANG YANG | | | | |
2019 | Micro-Architecture Optimization for Low-Power Bitcoin Mining ASICs. | CHIA-HSIANG YANG ; Wang, Yu-Zhe; Wu, Jingjie; Chen, Shi-Hao; Chao, Mango Chia-Tso; CHIA-HSIANG YANG | International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019, Hsinchu, Taiwan, April 22-25, 2019 | | | |
2016 | Multiple Input Multiple Output Wireless Communication System and Channel Decomposition Method Thereof | C.-H. Yang; Y.-C. Tsai; CHIA-HSIANG YANG | | | | |
2016 | Multiple Input Multiple Output Wireless Communication System and Channel Decomposition Method Thereof | C.-H. Yang; Y.-C. Tsai; CHIA-HSIANG YANG | | | | |
2018 | Performance of pre-production band 1 receiver for the Atacama Large Millimeter/submillimeter Array (ALMA) | Huang Y.-D.T; Morata O; Koch P.M; Kemper C; Hwang Y.-J; Chiong C.-C; Ho P.T.P; Chu Y.-H; Huang C.-D; Liu C.-T; Hsieh F.-C; Tseng Y.-H; CHIA-HSIANG YANG ; Tsay J.J; Chang T; Ho C.-T; Chiang P.-H; Chang C.-C; Jian S.-T; Hsu S.-P; Chien C; Iguchi S; Asayama S; Iono D; Gonzalez A; Effland J; Saini K; Pospieszalski M; Henke D; Yeung K; Finger R; Tapia V; Reyes N. | Proceedings of SPIE - The International Society for Optical Engineering | 5 | 0 | |
2012 | Power and area minimization of reconfigurable FFT processors: A 3GPP-LTE example | CHIA-HSIANG YANG ; Yang, C.-H.; Yu, T.-H.; Markovi?, D.; CHIA-HSIANG YANG | IEEE Journal of Solid-State Circuits | | | |
2013 | Power and area reduction in multi-stage addition using operand segmentation | CHIA-HSIANG YANG ; Chan, C.-D.; Liu, W.-C.; Yang, C.-H.; Jou, S.-J.; CHIA-HSIANG YANG | 2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013 | | | |
2020 | Pressure-impedance analysis: Assist the diagnosis and classification of ineffective esophageal motility disorder | JIA-FENG WU ; I-JUNG TSAI ; Tong, TW; YI-CHENG LIN ; CHIA-HSIANG YANG ; PING-HUEI TSENG | JOURNAL OF GASTROENTEROLOGY AND HEPATOLOGY | 4 | 3 | |
2020 | Radiation-Harden RISC Processor for Micro-Satellites in Standard CMOS | CHIA-HSIANG YANG ; Chiueh, H.; Yang, C.-H.; Wen, C.H.-P.; Yang, C.-G.; Chien, P.-H.; Hung, C.-Y.; Chen, Y.-J.; Wang, Y.-P.; Chiu, C.-F.; Lin, J.; CHIA-HSIANG YANG | 2020 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2020 | | | |
2016 | Sampling Circuit and Master-Slave Flip-Flop | S.-J. Jou; C.-H. Yang; W.-C. Liu; C.-W. Lo; C.-D. Chan; CHIA-HSIANG YANG | | | | |
2016 | sBWT: Memory Efficient Implementation of the Hardware-acceleration-friendly Schindler Transform for the Fast Biological Sequence Mapping | C.-H. Chang; M.-T. Chou; Y.-C. Wu; T.-W. Hong; Y.-L. Li; C.-H. Yang; J.-H. Hung; CHIA-HSIANG YANG | Bioinformatics | 8 | 7 | |
2014 | Unequal Bit-reliability Information Storage Method for Communication and Storage Systems | Y.-L. Ueng; C.-H. Yang; M. R. Li; CHIA-HSIANG YANG | | | | |