公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
2002 | Inductance modeling for on-chip interconnects | Tu, S.-W.; Shen, W.-Z.; Chang, Y.-W.; Chen, T.-C.; YAO-WEN CHANG | Proceedings - IEEE International Symposium on Circuits and Systems | 2 | 0 | |
2002 | Inductance modeling for on-chip interconnects | Tu, S.-W.; Shen, W.-Z.; Chang, Y.-W.; Chen, T.-C.; YAO-WEN CHANG | IEEE International Symposium on Circuits and Systems | 2 | | |
2007 | An Integer Linear Programming Based Routing Algorithm for Flip-Chip Design. | Fang, Jia-Wei; Hsu, Chin-Hsiung; Chang, Yao-Wen; YAO-WEN CHANG | Proceedings of the 44th Design Automation Conference, DAC 2007, San Diego, CA, USA, June 4-8, 2007 | 0 | 0 | |
2017 | An integrated-spreading-based macro-refining algorithm for large-scale mixed-size circuit designs | Chen, S.-T.; Chang, Y.-W. ; Chen, T.-C. | IEEE/ACM International Conference on Computer-Aided Design | 4 | 0 | |
2004 | Integrating buffer planning with floorplanning for simultaneous multi-objective optimization | Cheng, Y.-H.; Chang, Y.-W.; YAO-WEN CHANG | Asia and South Pacific Design Automation Conference, ASP-DAC | 8 | | |
2004 | Integrating buffer planning with floorplanning for simultaneous multi-objective optimization. | Cheng, Yi-Hui; Chang, Yao-Wen; YAO-WEN CHANG | Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, Yokohama, Japan, January 27-30, 2004 | 0 | 0 | |
2020 | Intelligent Design Automation for 2.5/3D Heterogeneous SoC Integration | Jiang I.H.-R; Chang Y.-W; Huang J.-L; CHUNG-PING CHEN ; HUI-RU JIANG ; JIUN-LANG HUANG ; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD | 5 | 0 | |
2017 | An Interview With Professor Chenming Hu, Father of 3D Transistors | Chang, Yao-Wen; Hu, Chenming; YAO-WEN CHANG | Ieee Design & Test | 0 | 0 | |
2009 | Introduction | Stroud, C.E.; Wang, L.T.; Chang, Y.-W.; YAO-WEN CHANG | Electronic Design Automation | 2 | 0 | |
2005 | Joint exploration of architectural and physical design spaces with thermal consideration. | Wu, Yen-Wei; Yang, Chia-Lin; Yuh, Ping-Hung; CHIA-LIN YANG ; YAO-WEN CHANG | Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005, San Diego, California, USA, August 8-10, 2005 | 18 | 0 | |
2020 | Latch clustering for timing-power co-optimization | Huang, C.-C.; Tellez, G.; Nam, G.-J.; YAO-WEN CHANG | Proceedings - Design Automation Conference | 2 | 0 | |
2023 | Late Breaking Results: An Efficient Bridge-based Compression Algorithm for Topologically Quantum Error Corrected Circuits | Tseng, Wei Hsiang; YAO-WEN CHANG | Proceedings - Design Automation Conference | 0 | 0 | |
2023 | Late Breaking Results: Analytical Placement for 3D ICs with Multiple Manufacturing Technologies | Chen, Yan Jen; Chen, Yan Syuan; Tseng, Wei Che; Chiang, Cheng Yu; Lo, Yu Hsiang; YAO-WEN CHANG | Proceedings - Design Automation Conference | 0 | 0 | |
2022 | Late Breaking Results: Flexible Chip Placement via Reinforcement Learning | Chang, Fu Chieh; Tseng, Yu Wei; Yu, Ya Wen; Lee, Ssu Rui; Cioba, Alexandru; Tseng, I. Lun; Shiu, Da Shan; Hsu, Jhih Wei; Wang, Cheng Yuan; Yang, Chien Yi; Wang, Ren Chu; YAO-WEN CHANG ; Chen, Tai Chen; Chen, Tung Chieh | Proceedings - Design Automation Conference | 0 | 0 | |
2022 | Late Breaking Results: Subgraph Matching Based Reference Placement for PCB Designs | Su, Miaodi; Xiao, Yifeng; Zhang, Shu; Su, Haiyuan; Xu, Jiacen; He, Huan; Zhu, Ziran; Chen, Jianli; YAO-WEN CHANG | Proceedings - Design Automation Conference | 0 | 0 | |
2013 | Layer minimization in escape routing for staggered-pin-array PCBs | Ho, Y.-K.; Shih, X.-W.; Chang, Y.-W.; Cheng, C.-K.; YAO-WEN CHANG | Asia and South Pacific Design Automation Conference, ASP-DAC | 5 | 0 | |
2015 | Layout decomposition for Spacer-is-Metal (SIM) self-aligned double patterning | Fang, S.-Y.; Tai, Y.-S.; Chang, Y.-W.; YAO-WEN CHANG | 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015 | 7 | 0 | |
2004 | Layout techniques for on-chip interconnect inductance reduction | Tu, S.-W.; Jou, J.-Y.; Chang, Y.-W.; YAO-WEN CHANG | Asia and South Pacific Design Automation Conference, ASP-DAC | 1 | | |
2004 | Layout techniques for on-chip interconnect inductance reduction. | Tu, Shang-Wei; Jou, Jing-Yang; Chang, Yao-Wen; YAO-WEN CHANG | Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, Yokohama, Japan, January 27-30, 2004 | 0 | 0 | |
2016 | Layout-Dependent Effects-Aware Analytical Analog Placement | Ou, H.-C.; Tseng, K.-H.; Liu, J.-Y.; Wu, I.-P.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 44 | 37 | |