公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
2006 | Modern floorplanning based on B*-tree and fast simulated annealing | Chen, T.-C.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 117 | 79 | |
2006 | Modern Floorplanning Based on B?-Tree and
Fast Simulated Annealing | Chen, Tung-Chieh; Chang, Yao-Wen | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | | | |
2005 | Modern floorplanning based on fast simulated annealing | Chen, T.-C.; Chang, Y.-W.; YAO-WEN CHANG | International Symposium on Physical Design | 59 | | |
2005 | Modern floorplanning based on fast simulated annealing. | Chen, Tung-Chieh; Chang, Yao-Wen; YAO-WEN CHANG | Proceedings of the 2005 International Symposium on Physical Design, ISPD 2005, San Francisco, California, USA, April 3-6, 2005 | 59 | 0 | |
2002 | Module placement with boundary constraints using B*-trees | Lin, J.-M.; Yi, H.-E.; YAO-WEN CHANG | IEE Proceedings: Circuits, Devices and Systems | 18 | 11 | |
2007 | MP-trees: A packing-based macro placement algorithm for mixed-size designs | Chen, T.-C.; Yuh, P.-H.; Chang, Y.-W.; Huang, F.-J.; Liu, D.; YAO-WEN CHANG | Design Automation Conference | 14 | 0 | |
2007 | MP-trees: A Packing-Based Macro Placement Algorithm for Mixed-Size Designs. | Chen, Tung-Chieh; Yuh, Ping-Hung; Chang, Yao-Wen; Huang, Fwu-Juh; Liu, Denny; YAO-WEN CHANG | Proceedings of the 44th Design Automation Conference, DAC 2007, San Diego, CA, USA, June 4-8, 2007 | 0 | 0 | |
2008 | MP-trees: A packing-based macro placement algorithm for modern mixed-size designs | Chen, T.-C.; Yuh, P.-H.; Chang, Y.-W.; Huang, F.-J.; Liu, T.-Y.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 30 | 27 | |
2004 | MR: A New Framework for Multilevel Full-Chip Routing | YAO-WEN CHANG ; Lin, Shih-Ping | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 40 | 34 | |
2008 | Multi-layer global routing considering via and wire capacities | Hsu, C.-H.; Chen, H.-Y.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design | 28 | 0 | |
2010 | Multilayer global routing with via and wire capacity considerations | Hsu, C.-H.; Chen, H.-Y.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 17 | 16 | |
2008 | Multilayer obstacle-avoiding rectilinear steiner tree construction based on spanning graphs | Lin, C.-W.; Huang, S.-L.; Hsu, K.-C.; Lee, M.-X.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 18 | 21 | |
2003 | Multilevel floorplanning/placement for large-scale modules using B*-trees | Lee, H.-C.; Chang, Y.-W.; Hsu, J.-M.; Yang, H.H.; YAO-WEN CHANG | Design Automation Conference | 28 | | |
2003 | Multilevel floorplanning/placement for large-scale modules using B*-trees. | Lee, Hsun-Cheng; Chang, Yao-Wen; Hsu, Jer-Ming; Yang, Hannah Honghua; YAO-WEN CHANG | Proceedings of the 40th Design Automation Conference, DAC 2003, Anaheim, CA, USA, June 2-6, 2003 | 0 | 0 | |
2005 | Multilevel full-chip gridless routing considering optical proximity correction | Chen, T.-C.; Chang, Y.-W.; YAO-WEN CHANG | Asia and South Pacific Design Automation Conference, ASP-DAC | 20 | | |
2005 | Multilevel full-chip gridless routing considering optical proximity correction. | Chen, Tai-Chen; Chang, Yao-Wen; YAO-WEN CHANG | Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005 | 20 | 0 | |
2007 | Multilevel full-chip gridless routing with applications to optical-proximity correction | Chen, T.-C.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 19 | 13 | |
2007 | Multilevel Full-Chip Gridless Routing With Applications to Optical-Proximity Correction | Chen, Tai-Chen; Chang, Yao-Wen | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | | 13 | |
2005 | Multilevel full-chip routing for the X-based architecture | Ho, Tsung-Yi; Chang, Chen-Feng; Chang, Yao-Wen ; Chen, Sao-Jie | Design Automation Conference | | | |
2005 | Multilevel full-chip routing for the X-based architecture. | SAO-JIE CHEN ; Chang, Chen-Feng; YAO-WEN CHANG ; Ho T.-Y | Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005 | 39 | 0 | |