公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
2011 | Thermal-driven analog placement considering device matching | Lin, M.P.-H.; Zhang, H.; Wong, M.D.F.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 26 | 20 | |
2009 | Thermal-driven analog placement considering device matching | Lin, P.-H.; Zhang, H.; Wong, M.D.F.; Chang, Y.-W.; YAO-WEN CHANG | Design Automation Conference | 26 | | |
2009 | Thermal-driven analog placement considering device matching. | Lin, Mark Po-Hung; Zhang, Hongbo; Wong, Martin D. F.; Chang, Yao-Wen; YAO-WEN CHANG | Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009 | 26 | 0 | |
2007 | Thermal-driven interconnect optimization by simultaneous gate and wire sizing | Lin, Y.-W.; Chang, Y.-W.; YAO-WEN CHANG | 2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 | 0 | 0 | |
2010 | Three-dimensional integrated circuits (3D IC) floorplan and power/ground network co-synthesis | Falkenstern, P.; Xie, Y.; Chang, Y.-W.; Wang, Y.; YAO-WEN CHANG | Asia and South Pacific Design Automation Conference, ASP-DAC | 55 | 0 | |
2021 | Time-Division Multiplexing Based System-Level FPGA Routing | Liu W.-K; Chen M.-H; Chang C.-M; Chang C.-C; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD | 0 | 0 | |
2020 | Time-division multiplexing based system-level FPGA routing for logic verification | Zou, P.; Lin, Z.; Shi, X.; Wu, Y.; Chen, J.; Yu, J.; YAO-WEN CHANG | Proceedings - Design Automation Conference | 5 | 0 | |
2012 | Timing ECO optimization using metal-configurable gate-array spare cells | Chang, H.-Y.; Jiang, I.H.-R.; YAO-WEN CHANG ; HUI-RU JIANG | Proceedings - Design Automation Conference | 4 | 0 | |
2011 | Timing ECO optimization via B?zier curve smoothing and fixability identification | Chang, H.-Y.; Jiang, I.H.-R.; YAO-WEN CHANG ; HUI-RU JIANG | IEEE/ACM International Conference on Computer-Aided Design | 2 | 0 | |
2012 | Timing ECO optimization via B?zier curve smoothing and fixability identification | Chang, H.-Y.; Jiang, I.H.-R.; YAO-WEN CHANG ; HUI-RU JIANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 11 | 9 | |
2004 | Timing modeling and optimization under the transmission line model | Chen, Tai-Chen; Pan, Song-Ra; Chang, Yao-Wen | IEEE Transactions on | 32 | 27 | |
2021 | Timing-Aware Fill Insertions with Design-Rule and Density Constraints | Bai X; Zhu Z; Li P; Chen J; Lan T; Li X; Yu J; Zhu W; Chang Y.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 0 | 0 | |
2019 | Timing-aware fill insertions with design-rule and density constraints | Lan T; Li X; Chen J; Yu J; He L; Dong S; Zhu W; Chang Y.-W.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD | 2 | 0 | |
2016 | Timing-Driven Cell Placement Optimization for Early Slack Histogram Compression | C. C. Huang; Y. C. Liu; Y. S. Lu; Y. C. Kuo; Y. W. Chang; S. Y. Kuo; SY-YEN KUO ; YAO-WEN CHANG | 53th ACM/IEEE Design Automation Conference (DAC-2016) | 9 | 0 | |
2000 | Timing-driven routing for symmetrical array-based FPGAs | Zhu, K.; Wong, D.F.; YAO-WEN CHANG | ACM Transactions on Design Automation of Electronic Systems | 23 | 20 | |
1998 | Timing-driven routing for symmetrical-array-based FPGAs | Zhu, Kai; Chang, Yao-Wen; Wong, D.F.; YAO-WEN CHANG | IEEE International Conference on Computer Design: VLSI in Computers and Processors | 10 | | |
2000 | Timing-driven routing for symmetrical-array-based FPGAs | CHANG, YAO-WEN ; ZHU, KAI; WONG, D. F. | ACM Transactions on Design Automation of Electronic Systems | | | |
1998 | Timing-driven routing for symmetrical-array-based FPGAs. | Zhu, Kai; Chang, Yao-Wen; Wong, D. F.; YAO-WEN CHANG | International Conference on Computer Design: VLSI in Computers and Processors, ICCD 1998, Proceedings, 5-7 October, 1998, Austin, TX, USA | 10 | 0 | |
2021 | Topological Structure and Physical Layout Co-design for Wavelength-Routed Optical Networks-on-Chip | Lu Y; Chen Y; Yu S; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 2 | 2 | |
2020 | Topological structure and physical layout codesign for wavelength-routed optical networks-on-chip | Lu, Y.-S.; Yu, S.-J.; YAO-WEN CHANG | Proceedings - Design Automation Conference | 6 | 0 | |