| Issue Date | Title | Author(s) | Source | scopus | WOS | Fulltext/Archive link |
| 2000 | B * -trees: A new representation for non-slicing floorplans | Chang, Y.-C.; Chang, Y.-W.; Wu, G.-M.; Wu, S.-W.; YAO-WEN CHANG | Proceedings-Design Automation Conference | 452 | 0 | |
| 2000 | B*-Trees: a new representation for non-slicing floorplans. | Chang, Yun-Chih; Chang, Yao-Wen; Wu, Guang-Ming; Wu, Shu-Wei; YAO-WEN CHANG | Proceedings of the 37th Conference on Design Automation, Los Angeles, CA, USA, June 5-9, 2000. | 0 | 0 | |
| 2000 | B<sup>*</sup>-trees: a new representation for non-slicing floorplans | Chang, Yun-Chih; Chang, Yao-Wen; Wu, Guang-Ming; Wu, Shu-Wei; YAO-WEN CHANG | Design Automation Conference | 452 | | |
| 2018 | beta-Nitrostyrene derivatives attenuate LPS-mediated acute lung injury via the inhibition of neutrophil-platelet interactions and NET release | Chang, Yao-Wen; Tseng, Ching-Ping; Lee, Chih-Hsun; Hwang, Tsong-Long; Chen, Yu-Li; Su, Mei-Tzu; Chong, Kowit-Yu; Lan, Ying-Wei; Wu, Chin-Chung; Chen, Kung-Ju; Lu, Fen-Hua; Liao, Hsiang-Ruei; Hsueh, Chuen; Hsieh, Pei-Wen; YAO-WEN CHANG | American Journal of Physiology-Lung Cellular and Molecular Physiology | 7 | 5 | |
| 2019 | BiG: A bivariate gradient-based wirelength model for analytical circuit placement | Sunl, F.-K.; Chang, Y.-W.; YAO-WEN CHANG | Proceedings - Design Automation Conference | 1 | 0 | |
| 2019 | BiG: A Bivariate Gradient-Based Wirelength Model for Analytical Circuit Placement. | Sun, Fan-Keng; Chang, Yao-Wen; YAO-WEN CHANG | Proceedings of the 56th Annual Design Automation Conference 2019, DAC 2019, Las Vegas, NV, USA, June 02-06, 2019 | 0 | 0 | |
| 2007 | Bioroute: A Network-Flow Based Routing Algorithm for Digital Microfluidic Biochips | Yuh, Ping-Hung; Yang, Chia-Lin ; CHIA-LIN YANG | IEEE/ACM International Conference on Computer-Aided Design | 80 | 0 |  |
| 2008 | BioRoute: A network-flow-based routing algorithm for the synthesis of digital microfluidic biochips | Yuh, Ping-Hung; YAO-WEN CHANG ; CHIA-LIN YANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 73 | 52 |  |
| 2009 | BIST design optimization for large-scale embedded memory cores | Chien, T.-F.; Chao, W.-C.; Li, C.-M.; Chang, Y.-W.; Liao, K.-Y.; Chang, M.-T.; Tsai, M.-H.; Tseng, C.-M.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design | 7 | | |
| 2009 | BIST design optimization for large-scale embedded memory cores. | Chien, Tzuo-Fan; Chao, Wen-Chi; Li, James Chien-Mo; Chang, Yao-Wen; Liao, Kuan-Yu; Chang, Ming-Tung; Tsai, Min-Hsiu; CHIEN-MO LI ; YAO-WEN CHANG | 2009 International Conference on Computer-Aided Design, ICCAD 2009, San Jose, CA, USA, November 2-5, 2009 | 7 | 0 | |
| 2010 | Blockage-avoiding buffered clock-tree synthesis for clock latency-range and skew minimization | Shih, X.-W.; Cheng, C.-C.; Ho, Y.-K.; Chang, Y.-W.; YAO-WEN CHANG | Asia and South Pacific Design Automation Conference, ASP-DAC | 23 | 0 | |
| 2017 | Blockage-aware terminal propagation for placement wirelength minimization | Yang, S.-W.; Chang, Y.-W. ; Chen, T.-C. | IEEE/ACM International Conference on Computer-Aided Design | 0 | 0 | |
| 2021 | A Bridge-based Compression Algorithm for Topological Quantum Circuits | Hsu C.-H; Lin W.-H; Tseng W.-H; YAO-WEN CHANG | Proceedings - Design Automation Conference | 2 | 0 | |
| 2014 | Buffered clock tree synthesis considering self-heating effects | Lin, C.-W.; Hsu, T.-H.; Shih, X.-W.; Chang, Y.-W.; YAO-WEN CHANG | International Symposium on Low Power Electronics and Design | 1 | 0 | |
| 2015 | Buffered clock tree synthesis considering self-heating effects | Lin, C.-W.; Hsu, T.-H.; Shih, X.-W.; Chang, Y.-W.; YAO-WEN CHANG | International Symposium on Low Power Electronics and Design | 0 | 0 | |
| 2014 | Buffered clock tree synthesis considering self-heating effects. | Lin, Chung-Wei; Hsu, Tzu-Hsuan; Shih, Xin-Wei; YAO-WEN CHANG ; CHUNG-WEI LIN | International Symposium on Low Power Electronics and Design, ISLPED'14, La Jolla, CA, USA - August 11 - 13, 2014 | 0 | 0 | |
| 2007 | Challenges and solutions in modern VLSI placement | Jiang, Z.-W.; Chen, H.-.; Chen, T.-C.; Chang, Y.-W.; YAO-WEN CHANG | 2007 International Symposium on VLSI Design, Automation and Test | 6 | 0 | |
| 2006 | Charge-based capacitance measurement for bias-dependent capacitance | Chang, Y.-W.; Chang, H.-W.; Lu, T.-C.; King, Y.-C.; Ting, W.; Ku, Y.-H.J.; Lu, C.-Y.; YAO-WEN CHANG | IEEE Electron Device Letters | 44 | 36 | |
| 2016 | Circular-contour-based obstacle-aware macro placement | Chiou, C.-H.; Chang, C.-H.; Chen, S.-T.; Chang, Y.-W.; YAO-WEN CHANG | Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC | 12 | 0 | |
| 2020 | Clock-Aware Placement for Large-Scale Heterogeneous FPGAs | Chen J; Lin Z; Kuo Y.-C; Huang C.-C; Chang Y.-W; Chen S.-C; Chiang C.-H; Kuo S.-Y.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 10 | 5 | |
