| Issue Date | Title | Author(s) | Source | scopus | WOS | Fulltext/Archive link |
| 2019 | A DAG-based algorithm for obstacle-aware topology-matching on-track bus routing | Hsu, C.-H.; Hungz, S.-C.; Chenz, H.; Sunz, F.-K.; Chang, Y.-W.; YAO-WEN CHANG | Proceedings - Design Automation Conference | 1 | 0 | |
| 2021 | A DAG-Based Algorithm for Obstacle-Aware Topology-Matching On-Track Bus Routing | Hsu C.-H; Hung S.-C; Chen H; Sun F.-K; Chang Y.-W.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 2 | 1 | |
| 2019 | A DAG-Based Algorithm for Obstacle-Aware Topology-Matching On-Track Bus Routing. | Hsu, Chen-Hao; Hung, Shao-Chun; Chen, Hao; Sun, Fan-Keng; Chang, Yao-Wen; YAO-WEN CHANG | Proceedings of the 56th Annual Design Automation Conference 2019, DAC 2019, Las Vegas, NV, USA, June 02-06, 2019 | 0 | 0 | |
| 2005 | Delay modeling for buffered RLY/RLC trees | Wang, S.-L.; Chang, Y.-W.; YAO-WEN CHANG | 2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test | 14 | 0 | |
| 2010 | Density gradient minimization with coupling-constrained dummy fill for CMP control | Chen, H.-Y.; Chou, S.-J.; Chang, Y.-W.; YAO-WEN CHANG | International Symposium on Physical Design | 19 | 0 | |
| 1995 | Design and analysis of FPGA/FPIC switch modules. | Wong, D. F.; Wong, C. K.; YAO-WEN CHANG | Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors | 5 | 0 | |
| 2014 | Design and Implementation of a RESTful Notification Service. | Chang, Yao-Wen; Sheu, Ruey-Kai; Jhu, Syuan-Ru; Chang, Yue-Shan; YAO-WEN CHANG | Intelligent Systems and Applications - Proceedings of the International Computer Symposium (ICS) held at Taichung, Taiwan, December 12-14, 2014 | 0 | 0 | |
| 2010 | Design of an Omnidirectional Multibeam Transmitter for High-Speed Indoor Wireless Communications. | Tang, Jaw-Luen; Chang, Yao-Wen; YAO-WEN CHANG | EURASIP J. Wireless Comm. and Networking | 3 | 0 | |
| 2010 | Design-hierarchy aware mixed-size placement for routability optimization | Chuang, Y.-L.; Nam, G.-J.; Alpert, C.J.; Chang, Y.-W.; Roy, J.; Viswanathan, N.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design | 25 | 0 | |
| 2017 | Detailed Placement for Two-Dimensional Directed Self-Assembly Technology | Lin, Z.-W.; Chang, Y.-W. | Design Automation Conference | 2 | 0 | |
| 2016 | Detailed-routability-driven analytical placement for mixed-size designs with technology and region constraints | Huang, C.-C.; Lee, H.-Y.; Lin, B.-Q.; Yang, S.-W.; Chang, C.-H.; Chen, S.-T.; Chang, Y.-W.; YAO-WEN CHANG | 2015 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2015 | 16 | 0 | |
| 2015 | Detailed-Routing-Driven analytical standard-cell placement | Huang, C.-C.; Chiou, C.-H.; Tseng, K.-H.; Chang, Y.-W.; YAO-WEN CHANG | 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015 | 16 | 0 | |
| 2013 | Double patterning lithography-aware analog placement | Chien, H.-C.C.; Ou, H.-C.; Chen, T.-C.; Kuan, T.-Y.; Chang, Y.-W.; YAO-WEN CHANG | Design Automation Conference | 7 | 0 | |
| 2016 | Double-patterning aware DSA template guided cut redistribution for advanced 1-D gridded designs | Lin, Z.-W.; Chang, Y.-W.; YAO-WEN CHANG | International Symposium on Physical Design | 18 | 0 | |
| 2019 | DSA-Compliant Routing for 2-D Patterns Using Block Copolymer Lithography | Su, Y.-H.; Chang, Y.-W. | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 0 | 0 | |
| 2016 | DSA-compliant routing for two-dimensional patterns using block copolymer lithography | Su, Y.-H.; Chang, Y.-W. | IEEE/ACM International Conference on Computer-Aided Design | 3 | 0 | |
| 2018 | DSA-Friendly detailed routing considering double patterning and DSA template assignments | Yu, H.-J.; Chang, Y.-W. | Design Automation Conference | 4 | 0 | |
| 2018 | DSA-Friendly detailed routing considering double patterning and DSA template assignments | Yu, H.-J.; Chang, Y.-W. | Design Automation Conference | 4 | 0 | |
| 2013 | ECO optimization using metal-configurable gate-array spare cells | Chang, H.-Y.; Jiang, I.H.-R.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 2 | 2 | |
| 2013 | ECO optimization using metal-configurable gate-array spare cells | Chang, H.-Y.; Jiang, I.H.-R.; YAO-WEN CHANG ; HUI-RU JIANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 2 | 2 | |
