| Issue Date | Title | Author(s) | Source | scopus | WOS | Fulltext/Archive link |
| 2020 | Hamiltonian path based mixed-cell-height legalization for neighbor diffusion effect mitigation | Chen, J.; Zhu, Z.; Liu, Q.; Zhang, Y.; Zhu, W.; YAO-WEN CHANG | Proceedings - Design Automation Conference | 2 | 0 | |
| 2011 | Heterogeneous B*-trees for analog placement with symmetry and regularity considerations | Chou, P.-Y.; Ou, H.-C.; Chang, Y.-W.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design | 24 | 0 | |
| 2011 | Hierarchical placement with layout constraints | Lin, M.P.-H.; Chang, Y.-W.; YAO-WEN CHANG | Analog Layout Synthesis: A Survey of Topological Approaches | 3 | 0 | |
| 2010 | High variation-tolerant obstacle-avoiding clock mesh synthesis with symmetrical driving trees | Shiht, X.-W.; Leet, H.-C.; Hot, K.-H.; Chang, Y.-W.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design | 23 | 0 | |
| 2009 | High-performance global routing with fast overflow reduction | Qien, H.-Y.; Hsu, C.-H.; Chang, Y.-W.; YAO-WEN CHANG | Asia and South Pacific Design Automation Conference, ASP-DAC | 58 | 0 | |
| 2006 | A high-quality mixed-size analytical placer considering preplaced blocks and density constraints. | Chen, Tung-Chieh; Jiang, Zhe-Wei; Hsu, Tien-Chang; Chen, Hsin-Chen; Chang, Yao-Wen; YAO-WEN CHANG | 2006 International Conference on Computer-Aided Design, ICCAD 2006, San Jose, CA, USA, November 5-9, 2006 | 0 | 0 | |
| 2015 | Identification of a novel platelet antagonist that binds to CLEC-2 and suppresses podoplanin-induced platelet aggregation and cancer metastasis | Chang, Yao-Wen; Hsieh, Pei-Wen; Chang, Yu-Tsui; Lu, Meng-Hong; TUR-FU HUANG ; Chong, Kowit-Yu; Liao, Hsiang-Ruei; Cheng, Ju-Chien; YAO-WEN CHANG | Oncotarget | 68 | 58 | |
| 2006 | IEEE standard 1500 compatible interconnect diagnosis for delay and crosstalk faults | Li, K.S.-M.; Su, C.; Lee, C.-L.; Chen, J.E.; YAO-WEN CHANG | Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC | 0 | | |
| 2006 | IEEE standard 1500 compatible interconnect diagnosis for delay and crosstalk faults | Li, K.S.-M.; Su, C.; Lee, C.-L.; Chen, J.E.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 11 | 9 |  |
| 2011 | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems: Guest Editorial | Saxena, P.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 0 | 0 | |
| 2014 | The IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2014, San Jose, CA, USA, November 3-6, 2014 | YAO-WEN CHANG | | | | |
| 2007 | An ILP algorithm for post-floorplanning voltage-island generation considering power-network planning. | Lee, Wan-Ping; Liu, Hung-Yi; Chang, Yao-Wen; YAO-WEN CHANG | 2007 International Conference on Computer-Aided Design, ICCAD 2007, San Jose, CA, USA, November 5-8, 2007 | 57 | 0 | |
| 2010 | ILP-based pin-count aware design methodology for microfluidic biochips | Lin, C.C.-Y.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 27 | 22 | |
| 2009 | ILP-based pin-count aware design methodology for microfluidic biochips. | Lin, Cliff Chiung-Yu; YAO-WEN CHANG | Proceedings - Design Automation Conference | 27 | 0 | |
| 2005 | IMF: Interconnect-driven multilevel floorplanning for large-scale building-module designs | Chen, T.-C.; Chang, Y.-W.; Lin, S.-C.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design | 41 | 0 | |
| 2006 | Inductance extraction for general interconnect structures | Lai, Chun-Ying; Jeng, Shyh-Kang ; Chang, Yao-Wen ; Tsai, Chia-Chun | International Symposium on Circuits and Systems, 2006. ISCAS '06 | 0 | 0 | |
| 2006 | Inductance extraction for general interconnect structures | Lai, C.-Y.; Jeng, S.-K.; Chang, Y.-W.; Tsai, C.-C.; YAO-WEN CHANG | IEEE International Symposium on Circuits and Systems | 0 | | |
| 2003 | Inductance Modeling for On-Chip Interconnects | Tu, Shang-Wei; Shen, Wen-Zen; Chang, Yao-Wen ; Chen, Tai-Chen; Jou, Jing-Yang | Analog Integrated Circuits and Signal Processing | 5 | 4 | |
| 2002 | Inductance modeling for on-chip interconnects | Tu, S.-W.; Shen, W.-Z.; Chang, Y.-W.; Chen, T.-C.; YAO-WEN CHANG | IEEE International Symposium on Circuits and Systems | 2 | | |
| 2002 | Inductance modeling for on-chip interconnects | Tu, S.-W.; Shen, W.-Z.; Chang, Y.-W.; Chen, T.-C.; YAO-WEN CHANG | Proceedings - IEEE International Symposium on Circuits and Systems | 2 | 0 | |
